Energy Efficient Computing in Nanoscale CMOS
IEEE Solid-State Circuits Society Distinguished Lecture
Future computing systems spanning exascale supercomputers to wearable devices demand orders of magnitude improvements in energy efficiency while providing desired performance. The system-on-chip (SoC) designs need to span a wide range of performance and power across diverse platforms and workloads. The designs must achieve robust near-threshold-voltage (NTV) operation in nanoscale CMOS process while supporting a wide voltage-frequency operating range with minimal impact on die cost. We will discuss circuit and design technologies to overcome the challenges posed by device parameter variations, supply noises, temperature excursions, aging-induced degradations, workload and activity changes, and reliability considerations. The major pillars of energy-efficient SoC designs are: (1) circuit/design optimizations for fine-grain multi-voltage & wide dynamic range, (2) fine-grain on-die power delivery & management, (3) dynamic adaptation & reconfiguration, (4) dynamic on-die error detection & correction, and (5) efficient interconnects.
Date and Time
Location
Hosts
Registration
- Date: 09 Mar 2018
- Time: 03:00 PM to 04:00 PM
- All times are (GMT-08:00) Canada/Pacific
-
Add Event to Calendar
- Electrical & Computer Engineering
- 2356 Main Mall
- Vancouver, British Columbia
- Canada V6T1Z4
- Building: Macleod
- Room Number: MCLD-418
- Contact Event Host
- Co-sponsored by Sudip Shekhar
- Starts 24 February 2018 08:14 PM
- Ends 09 March 2018 02:15 PM
- All times are (GMT-08:00) Canada/Pacific
- No Admission Charge
Speakers
Vivek De of Intel Corporation
Biography:
Vivek De is an Intel Fellow and Director of Circuit Technology Research in Intel Labs. He is responsible for providing strategic technical directions for long term research in future circuit technologies and leading energy efficiency research across the hardware stack. He has 267 publications in refereed international conferences and journals with a citation H-index of 68, and 219 patents issued with 31 more patents filed (pending). He received an Intel Achievement Award for his contributions to an integrated voltage regulator technology. He received a Best Paper Award at the 1996 IEEE International ASIC Conference, and nominations for Best Paper Awards at the 2007 IEEE/ACM Design Automation Conference (DAC) and 2008 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). He also co-authored a paper nominated for the Best Student Paper Award at the 2017 IEEE International Electron Devices Meeting (IEDM). One of his publications was recognized in the 2013 IEEE/ACM Design Automation Conference (DAC) as one of the "Top 10 Cited Papers in 50 Years of DAC". Another one of his publications received the “Most Frequently Cited Paper Award” in the IEEE Symposium on VLSI Circuits at its 30th Anniversary in 2017. He was recognized as a Prolific Contributor to the IEEE International Solid-State Circuits Conference (ISSCC) at its 60th Anniversary in 2013, and a Top 10 Contributor to the IEEE Symposium on VLSI Circuits at its 30th Anniversary in 2017 . He served as an IEEE/EDS Distinguished Lecturer in 2011 and an IEEE/SSCS Distinguished Lecturer in 2017-18. He received the 2017 Distinguished Alumnus Award from the Indian Institute of Technology (IIT) Madras. He received a B.Tech from IIT Madras, India, a MS from Duke University, Durham, North Carolina, and a PhD from Rensselaer Polytechnic Institute, Troy, New York, all in Electrical Engineering. He is a Fellow of the IEEE.