Heterogeneous 3D Integrated Circuits - Current Problems

#Integrated #circuits #3D #integration
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As the sizing of transistors comes to the atomic distance limitations further development becomes possible by either introduction of new technologies or changing in geormetric arrangements of the elements and building blocks. Limitations in microcircuit constructions can be avoided by putting whole building blocks and sub-circuits in 3-dimensional stacks. Such an approach allows for efficient space usage at the same time allowing circuit footprint reduction. Also routing solutions offer very significant wire-length reductions thus reducing power dissipations and signal delays. 3D integration looks as a fantastic area of development, however, there are many new challenges and problems to be solved. 3D integration offers also unprecedented opportunities by allowing blocks fabricated in heterogeneous technologies to be integrated in one chip. This allows for integration of microprocessors, memories, RF circuitry, sensors, batteries and hyper-capacitors, energy harvesting blocks, biological and chemical sensors and many new types of building blocks in one chip. Current state and new perspectives are discussed.



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  • Date: 07 May 2018
  • Time: 02:00 PM to 03:00 PM
  • All times are (GMT-08:00) America/Vancouver
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  • Simon Fraser University
  • 8888 University Drive
  • Burnaby, British Columbia
  • Canada V5A 1S6
  • Building: Applied Sciences Building
  • Room Number: ASB 10940 (SFU's Big Data Visualization Lab)
  • Click here for Map

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  • Ljiljana Trajkovic

  • Starts 04 March 2018 12:00 AM
  • Ends 07 May 2018 02:00 PM
  • All times are (GMT-08:00) America/Vancouver
  • No Admission Charge


  Speakers

Maciej Ogorzalek of #3563873

Topic:

Heterogeneous 3D Integrated Circuits - Current Problems

As the sizing of transistors comes to the atomic distance limitations further development becomes possible by either introduction of new technologies or changing in geormetric arrangements of the elements and building blocks. Limitations in microcircuit constructions can be avoided by putting whole building blocks and sub-circuits in 3-dimensional stacks. Such an approach allows for efficient space usage at the same time allowing circuit footprint reduction. Also routing solutions offer very significant wire-length reductions thus reducing power dissipations and signal delays. 3D integration looks as a fantastic area of development, however, there are many new challenges and problems to be solved. 3D integration offers also unprecedented opportunities by allowing blocks fabricated in heterogeneous technologies to be integrated in one chip. This allows for integration of microprocessors, memories, RF circuitry, sensors, batteries and hyper-capacitors, energy harvesting blocks, biological and chemical sensors and many new types of building blocks in one chip. Current state and new perspectives are discussed.

Biography:

Maciej J. Ogorzalek is Professor of Electrical Engineering and Computer Science and Head of the Department of Information Technologies, Jagiellonian University Krakow, Poland – the oldest (1364) higher education institution in the country.He held several visiting positions in Denmark, Switzerland, Germany, Spain, Japan, Hong Kong.He received a Research Award from the Ministry of Education of Spain in 2000 and worked for one year at the National Microelectronic Center, Sevilla, Spain. In 2001 he received a Senior Award from the Japan Society for Promotion of Science as visiting professor at Kyoto University and in 2005 Hertie Foundation Fellowship at The Goethe University Frankfurt-am-Main. 2006-2009 he held the Chair of Biosignals and Systems, Hong Kong Polytechnic University under the Distinguished Scholars Scheme. Author or co-author of over 350 technical papers published in journals and conference proceedings, author of the book Chaos and Complexity in Nonlinear Electronic Circuits (World Scientific, 1997). He gave over 40 plenary and keynote lectures at major conferences world-wide. He served as Editor-in-Chief of the Circuits and Systems Magazine 2004-2007, Associate Editor for the IEEE Transactions on Circuits and Systems Part I, 1993-1995 and 1999-2001, he was elected Member of the Editorial Board Proceedings of the IEEE 2004-2009. He serves also as an Associate Editor – Journal of the Franklin Institute (1997-), Member of the Editorial Board of the International Journal of Bifurcation and Chaos, Secretary of the Editorial Board for the Quarterly of Electrical Engineering (1993-2000), Member of the Editorial Board of Automatics (both in Polish), and Member of the Editorial board of the International Journal of Circuit Theory and Applications (2000- ) and Associate Editor of the NOLTA Journal IEICE Japan. Dr. Ogorzalek is IEEE Fellow (1997). He served the IEEE Circuits and Systems Society in various capacities including VP for Region 8, Administrative Vice-president and finally 2008 Society President. He was CAS Society Distinguished Lecturer (2004-2005) and received the 2002 Guillemin-Cauer Award, IEEE-CAS Golden Jubilee Award and IEEE CAS Meritorious Service Award. He served as IEEE Division 1 Director (2016-2017), Member of the IEEE Board of Directors. Until 2006 he was Executive Vice-President of the Sniadecki Science Foundation in Poland. He is Member of the Polish Academy of Sciences (PAN) and Member of the European Academy of Sciences (Academia Europaea).

Email:

Address:Department of Information Technologies, Faculty of Physics, Astronomy and Applied Computer Science, Jagiellonian University, Krakow, Poland