IEEE Dayton PEAL Technical Talk: In-the-Loop Testing of Power Electronics Systems

#hardware-in-the-loop #processor-in-the-loop #power #electronics #simulation #PLECS
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Manaswini Parimi, Applications Engineer at Plexim, Inc. (https://www.plexim.com/plecs) will give a talk on processor and hardware in the loop testing.  While the discussion will include a demonstration of their (PLECS) software, we have been assured that it will remain technical and relevant, with the primary objective to educate and not to sell.  PLECS will be provided for free to all attendees. The subject description is below.

Subject: Designing power converters and their associated control systems is a complex task requiring advanced tools and processes. Later stage testing can be difficult due to cost, resource and safety concerns. “In-the-loop” methodologies such as Processor-in-the-Loop (PIL) and Hardware-in-the-Loop (HIL) allow for tying prototype software and hardware subsystems into a high-fidelity, complete system test environment.

With PIL, embedded code can be executed on the actual embedded processor and co-simulated with a plant model. With the HIL approach a real-time simulation platform allows for the complete control system as the DUT as a precursor or replacement for experimental prototype hardware development. Several applications, including DC/DC converters, solar inverters, and motor drives will be explored via offline and real-time simulation examples.



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  • Date: 28 Mar 2018
  • Time: 06:00 PM to 08:00 PM
  • All times are (GMT-05:00) US/Eastern
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  • 1700 S Patterson Blvd
  • Dayton, Ohio
  • United States 45469
  • Building: University of Dayton Research Institute, River Campus

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Agenda

6:00 pm Light buffet and refreshments

6:15pm Presentation begins

Lecture Outline

 

  1. Importance of system modeling

 

  1. System modeling with PLECS

        Top-down design of complex systems

 

  1. Leveraging system models for control systems development General concepts

 

  1. Processor-In-the-Loop co-simulation (PIL) High fidelity testing at all switching frequencies Software test points Demo

 

  1. Hardware-In-the-Loop simulation (HIL) Plant code generation with PLECS


RSVP by March 19, 2018