The Case for Clock-power Unification in Next Generation Digital SoC Domains
Energy-efficient computing remains a principal performance- and feasibility-limiting concern across the broad range of computing applications, from near and sub-threshold IoT systems to High-performance Computing. Independent advances in the areas of clocking (through low-power clock generation and distribution, gating) and voltage regulation (Dynamic Voltage and Frequency Scaling, Integrated Voltage Regulation) have been key enablers to efficiency improvements in digital SoCs over the past couple of decades.
The benefits achieved by these techniques have, in recent years, saturated somewhat. The historically unheralded problem of voltage margins required in real-world SoCs -- to address aging , temperature variation (especially in low-power systems), and supply noise in particular -- has emerged as a salient contributor to inefficiency, sparking various efforts to address this challenge.
In this talk, I identify the synergies between the traditionally independent systems of clock and power delivery, and make the case for a unification of these systems to address the efficiency challenge. Through a discussion of test-chip results, I will demonstrate the promise of this approach, and highlight the challenges in the way of employing the approach to altogether eliminate voltage margins in digital systems.
http://www.ece.utexas.edu/events/case-clock-power-unification-next-generation-digital-soc-domains
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- Date: 18 Apr 2018
- Time: 03:00 PM to 04:00 PM
- All times are (UTC-05:00) Central Time (US & Canada)
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- Starts 10 April 2018 12:22 AM
- Ends 18 April 2018 03:00 PM
- All times are (UTC-05:00) Central Time (US & Canada)
- No Admission Charge
Speakers
Visvesh S. Sathe
The Case for Clock-power Unification in Next Generation Digital SoC Domains
Biography:
Visvesh S. Sathe joined the University of Washington Department of Electrical Engineering in 2013. Prior to joining the faculty at the University of Washington, he served as a Member of Technical Staff in the Low-Power Advanced
Development Group at AMD, where his research focused on inventing and developing new technologies for next-generation microprocessors. Dr. Sathe has led the research and development effort at AMD that resulted in the first-ever
resonant clocked commercial microprocessor. Several of his inventions in the area of high performance digital circuits and adaptive clocking for supply noise mitigation have been incorporated into current and next generation microprocessors. His research interests lie at the intersection of digital and mixed-signal circuits and architectures for energy efficient computing and bio-medical electronics.