Technology Circuit Co-Design for Nano-Scale Era / Distinguished Lecture
The lecture will be focused on technology pros and cons, variability impact, methods to evaluate it and circuit
aspects in co-design. Also clever usage of TCAD to predict device and circuit capacitances will be presented.
Date and Time
Location
Hosts
Registration
- Date: 03 Sep 2018
- Time: 10:00 AM to 11:30 PM
- All times are (UTC+02:00) Prague
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- CTU in Prague, FEE
- Technicka 2
- Praha 6, Czech Republic
- Czech Republic 16627
- Room Number: 80
- Click here for Map
Speakers
Dr. Rajiv Joshi of IBM
Technology Circuit Co-Design for Nano-Scale Era
The lecture will be focused on technology pros and cons, variability impact, methods to evaluate it and circuit
aspects in co-design. Also clever usage of TCAD to predict device and circuit capacitances will be presented.
Biography:
Rajiv V. Joshi is a research staff member and key technical lead at T. J. Watson research center, IBM. He received his
B.Tech I.I.T (Bombay, India), M.S (M.I.T) and Dr. Eng. Sc. (Columbia University). His novel interconnects processes
and structures for aluminum, tungsten and copper technologies which are widely used in IBM for various technologies
from sub-0.5 mm to 14 nm. He has led successfully predictive failure analytic techniques for yield prediction and also
the technology-driven SRAM at IBM Server Group. He is awarded prestigious IEEE Daniel Noble award for 2018. He
received the Best Editor Award from IEEE TVLSI journal. He is recipient of 2015 BMM award. He is inducted into New
Jersey Inventor Hall of Fame in Aug 2014 along with pioneer Nicola Tesla. He is a recipient of 2013 IEEE CAS Industrial
Pioneer award and 2013 Mehboob Khan Award from Semiconductor Research Corporation. He is a member of IBM
Academy of technology.