Designing Regenerative Comparators in CMOS for Low Offset and Noise
Dear IEEE Solid-State Circuit member in Switzerland,
For the second meeting of this year we propose a lecture of Pr. Abidi. on
"Designing Regenerative Comparators in CMOS for Low Offset and Noise"
Subthreshold or analog sub-1V power supplies operation, are getting famous for their energy efficiency due to voltage scaling effect.
The lecture discusses how to balance specifications on noise and offset with comparator delay and bit-error-rate in communications receivers.
We look forward meeting you in this second technical meeting of the year
Kind regards,
Mathieu Coustans
Secretary of the IEEE Solid State Circuit Switzerland Chapter.
Date and Time
Location
Hosts
Registration
- Date: 21 Mar 2019
- Time: 11:00 AM to 12:00 PM
- All times are (UTC+01:00) Bern
-
Add Event to Calendar
- EPFL
- 71, Rue de la Maladière
- Neuchatel, Switzerland
- Switzerland CH-2000
- Building: Microcity
- Room Number: MC A1 272
- Click here for Map
- Contact Event Host
-
Pr Enz.
Host of the event.
christian.enz@epfl.ch
- Co-sponsored by EPFL - ICLAB
- Starts 11 March 2019 02:00 PM
- Ends 21 March 2019 09:30 AM
- All times are (UTC+01:00) Bern
- No Admission Charge
Speakers
Pr. Abidi
Designing Regenerative Comparators in CMOS for Low Offset and Noise
We show that modern comparator circuits as used in A/D converters and communications receivers consist of an embedded dynamic amplifier followed by a cross-coupled regenerative sub-circuit. The dynamic amplifier usually has a large enough voltage gain that it determines the input offset and noise for the entire comparator.
The offset in this amplifier is both static and dynamic. A deliberate unbalance of internal capacitances can be exploited to null one form of offset with the other. The noise bandwidth of the dynamic amplifier is shown to be the inverse of its latency, which is usually independent of the regeneration time constant.
This work guides the design of a comparator circuit to balance specifications on noise and offset with comparator delay and bit error-rate. Further, it shows why one of the comparator topologies is preferred for operation at sub-1V power supplies.
Biography:
Asad Abidi received the BSc degree in Electrical Engineering from Imperial College, London in 1976, and the PhD from the University of California, Berkeley in 1982. He worked at Bell Laboratories, Murray Hill until 1985, and then joined the faculty of the University of California, Los Angeles where he is Distinguished Chancellor’s Professor of Electrical Engineering. With his students he has developed many of the radio circuits and architectures that enable today’s mobile devices.
Among other awards, Professor Abidi has received the 2008 IEEE Donald O. Pederson Award in Solid-State Circuits and the 2012 Best Paper Award from the IEEE Journal of Solid-State Circuits. The University of California, Berkeley’s Department of EECS recognized him as a Distinguished Alumnus in 2015. He was elected Fellow of IEEE in 1996, Member of the US National Academy of Engineering, and Fellow of TWAS, the world academy of sciences.
Professor Abidi also holds the Abdus Salam Chair at the SBA School of Science & Engineering, LUMS, Lahore.
Email:
Address:7400 Boelter Hall, , Los Angeles, California, United States, 90095