Salvatore Levantino

This tutorial will introduce the fundamentals of analysis and practical implementation of digital PLLs. Unlike analog loops, the design of digital PLLs should take into account quantization, which can potentially generate limit cycles and degrade the output spectrum. A full design flow to meet bandwidth and jitter specifications, avoiding limit cycles, will be illustrated, and a comparison between digital PLLs based on multi-bit, high-resolution time-to-digital converters and those based on bang-bang phase detectors, will be shown.

Biography:

Salvatore Levantino received the Ph.D. in electrical engineering from the Politecnico di Milano, Italy, in 2001. From 2000 to 2002, he was a consultant at Bell Labs, Lucent Technologies, Murray Hill, NJ. Since 2005, he has been an Assistant Professor and subsequently Associate Professor of electrical engineering at Politecnico di Milano. He coauthored 6 patents, more than 100 papers in international journals and conference proceedings, and the textbook “Integrated Frequency Synthesizers for Wireless Systems” (Cambridge Univ. Press, 2007). He was co-recipient of the best paper award at the 2018 International Symposium on Circuits and Systems (ISCAS). Dr. Levantino was guest editor for the IEEE Journal of Solid-State Circuits (2016) and associate editor for the IEEE Transactions on Circuits and Systems–I (2014-2015) and for the IEEE Transactions on Circuits and Systems–II (2012- 2013). He is a senior member of IEEE and a TPC member of the IEEE Radio Frequency Integrated Circuits (RFIC) and the IEEE European Solid-State Circuits Conference (ESSCIRC).