High Speed CMOS Serial Transmitters for 56-112Gb/s Electrical Interconnects

#CMOS #Serial #Transmitters #56-112GB/s

Abstract: Data rates in high-speed wireline communication links continue to increase, fueled by demands in data center and high-performance computing applications.  In recent years, serial link data rates have increased from 28Gb/s to 56Gb/s, with 112Gb/s rapidly approaching.  To achieve these higher data rates across high-loss electrical channels, standards are switching from NRZ to PAM4 signaling.  In this talk, we will start with an overview of serial transmitter architectures focusing on feed-forward equalization (FFE) techniques as well as power considerations for PAM4 links.  Next, we will look at the design of a 56-Gb/s PAM4 transmitter designed in 14nm FinFET CMOS technology with a fractionally-spaced FFE.  Finally we will look at future directions for 112Gb/s and discuss the design of a 112-Gb/s PAM4 transmitter in 14nm FinFET CMOS technology with precise equalization control to minimize intersymbolinterference in PAM4 links.

• Date: 09 Apr 2020
• Time: 04:30 PM to 05:30 PM
• All times are (GMT-05:00) US/Eastern
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• Princeton University
• Princeton, New Jersey
• United States 08550
• Building: Engineering Quad
• Room Number: B205

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