Test Technology for Heterogeneous Integration
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The Test Technology chapter of the new Roadmap highlights the challenges and opportunities for the semiconductor industry as we move forward. The chapter itself is divided into 15 different white papers because of the significant diversity of different challenges the test industry must face. Whether it’s a single cellphone SIP with incredible complexity or a use-once medical sensor where incredible accuracy is life-critical, the test industry must meet the needs. Dave Armstrong will deliver an overview, he will give brief updates on testing of photonic, memory, 2.5D, and specialty device testing. He will also discuss how system level test is improving test coverage at a reduced cost. Following will be updates on three of the fastest-changing areas of test.
With the significant recent increases in internet traffic, efficient testing of big-digital AI, server, and communications devices is more critical than ever before. Marc Hutner will discuss how logic test is confronting this challenge, including a discussion on how design-for-test (DFT) is both challenging and helping the industry as we move forward.
The roll out of 5G mobile phone devices is anticipated to be a world-changing advancement. Meeting this need requires many advances in the test technology of RF devices. Don Blair will provide an overview of how the test industry is changing in order to meet these challenges.
It is really difficult for the industry to maintain a cost-effective test cost when device complexity is growing in so rapidly and in so many directions. This makes it difficult to keep the cost-of-test from skyrocketing. Ken Lanier will discuss steps the industry is taking to meet these challenges and what the results and forecast is for device test costs.
Date and Time
Location
Hosts
Registration
- Date: 02 Jul 2020
- Time: 08:00 AM to 09:00 AM
- All times are (GMT-08:00) US/Pacific
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- Santa Clara, California
- United States
- Starts 29 June 2020 09:00 PM
- Ends 02 July 2020 09:00 AM
- All times are (GMT-08:00) US/Pacific
- No Admission Charge
Speakers
Dave of Advantest
Biography:
Dave Armstrong, in his capacity as Director of Business Development, works directly with customers and Advantest’s global R&D teams to define, develop and deliver creative solutions to the most demanding test challenges. Additionally, Dave is currently the Chairman of the Test Technology Working group for the Heterogeneous Integration Roadmap. Prior to joining Advantest in 2004, Dave spent over two decades in HP/Agilent’s IC test group achieving the role of Principal Engineer. Prior to joining HP Dave worked in the semiconductor industry in areas of IC and system design, product/yield engineering, as well as test engineering. Dave Armstrong received degrees in Electrical, Computer, and Environmental Engineering from the University of Michigan in 1974.
Kanad
Biography:
Ken Lanier is Co Chair of the HIR Test Technology Working Group.
Don Blair is a Business Development Manager working for Advantest for 33 years (HP > Agilent > Verigy > Advantest) and 5 years for Schlumberger before that. His experience base has been digital and mixed-signal testing starting with Series 10/20 and 80 and continuing on with the V93000 platform. He currently is the lead on the HIR TWG for the Analog Mixed Signal and RF teams.
Marc Hutner is the DfX Systems Engineering responsible for design to test solutions that accelerate ATE debug. He has worked at Teradyne for 20 years in a variety of engineering and technical management positions. This includes analog IP design, ASIC development management, Instrument design, ATE system definition and technical product management. He also is a contributor to the Heterogeneous Integration Roadmap for Semiconductors (formerly the ITRS roadmap) for test