RISC-V and VLSI Chip Design Roadshow
#RISC
#V
#VLSI
#Chip
#Design
#Roadshow
Introduction:
On April 12th, 2024, the RISC-V and VLSI Chip Design Roadshow Workshop took place at the Cambridge Institute of Technology. This event aimed to bridge the gap between theoretical knowledge and practical skills in the field of Very Large Scale Integration (VLSI) design using the RISC-V architecture.
Date and Time
Location
Hosts
Registration
- Start time: 11 Apr 2024 11:50 PM
- End time: 12 Apr 2024 11:52 PM
- All times are (UTC+05:30) Chennai
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- Department of ECE
- Cambridge Institute of Technology
- Bangalore, Karnataka
- India 560036
- Building: SIR M VBlock
- Room Number: J C Bose Seminar Hall & VLSI Lab
- Starts 05 April 2024 12:42 AM
- Ends 11 April 2024 12:46 AM
- All times are (UTC+05:30) Chennai
- No Admission Charge
Speakers
Mr Kunal ghosh of Director & Co-founder, VLSI System Design (VSD)
Topic:
RISC V & VLSI
Biography:
Director & Co-founder, VLSI System Design (VSD)
Media
| RISC-V and VLSI Chip Design Roadshow | 190.97 KiB |