Prof. Carlo Samori of Politecnico di Milano, Italy

Digital phase-locked loops (DPLLs) have emerged in the last ten years as an important alternative to analog PLLs, also for fractional-N synthesis in wireless applications where a very demanding spectral purity is required. While in the initial implementations the key building block of DPLLs was a multi-bit time to digital converter (TDC), which is a power consuming circuit analog to an ADC, record performance has been ultimately obtained by exploiting an architecture featuring a time arbiter, i.e., a single-bit TDC, driven by a multi bit digital-to-time converter (DTC). The key enabling idea is to exploit the dithering property of the thermal noise always present in a circuit. The presentation reviews the path that has led to this approach, which epitomize how scaled CMOS technologies may enable powerful calibration techniques achieving unprecedented performance.

Biography:

Carlo Samori received a Ph.D. in electrical engineering in 1995, from the Politecnico di Milano, Italy, where he is now a professor. His research interests are in the area of RF circuits, in particular of design and analysis of VCOs and high performance frequency synthesizers. He has collaborated with several semiconductor companies. He is a co-author of more than 100 papers and of the book Integrated Frequency Synthesizers for Wireless Systems (Cambridge University Press, 2007). Prof. Samori has been a member of the Technical Program Committee (TPC) of the IEEE International Solid-State Circuits Conference and he is a member of the TPC of the European Solid-State Circuits Conference. He has been a Guest Editor for the December 2014 issue of the Journal of Solid-State Circuits. Carlo Samori is a Distinguished Lecturer of the IEEE Solid-State Circuits Society and an IEEE Fellow.

Prof. Carlo Samori of Politecnico di Milano, Italy

Biography: