Dr. Jifa Hao of ON Semiconductor

Reliability failures become more and more complicated and difficult when the devices shrink in size and manufacturing complexities is increased. And market pressures are forcing shorter process development times even as the processes become more complex. Finding and correcting reliability problems early in the design and development cycle is much cheaper and faster than finding the problem during qualification. In order to reduce time-to-market, to reduce the cost, and to isolate individual failure mechanism, wafer level reliability (WLR) or process and device reliability test is needed. In this talk, we will briefly discuss built-in reliability as an integral part of the design and technology development process. Then we will discuss fundamental process and device reliability physics: hot carrier injection (HCI), time dependent dielectric breakdown (TTDB), electromigration, negative bias temperature instability (NBTI), and plasma process induced charge (PPIC).

Biography:

Jifa Hao (SM’01) received his Ph.D. in Physics from Stony Brook University. Currently he works for ON Semiconductor as MTS, and is responsible for process, device and new technology reliability. He has worked in the semiconductor industry for over 20 years in reliability R&D, technology development, and process development with Fairchild, Allegro Microsystems, Intersil and Harris Semiconductor.  He has authored or coauthored over 40 journal and conference papers and has presented many invited talks at IEEE conferences, Electrochemical Society conferences, and Universities. He holds 11 US patents. He is a committee member of IEEE EDS Device Reliability Physics, and is president of the Maine chapter of IEEE EDS/SSCS.

Email:

Address:333 Western Ave , , South Portland, Maine, United States

Dr. Jifa Hao of ON Semiconductor

Biography:

Email:

Address:South Portland, Maine, United States