BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Asia/Hong_Kong BEGIN:STANDARD DTSTART:19791021T023000 TZOFFSETFROM:+0900 TZOFFSETTO:+0800 TZNAME:HKT END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20171230T052130Z UID:33505C54-3D01-460F-880C-7AAF26CD45FA DTSTART;TZID=Asia/Hong_Kong:20170807T100000 DTEND;TZID=Asia/Hong_Kong:20170808T113000 DESCRIPTION:Although FPGA or hardware-based implementation of software can give us not only higher performance but also energy efficient computing\, efficient implementation algorithms as hardware and as software can be sig nificantly different. Typical high-level synthesis methods may not concent rate on this issue\, as they are targeting general hardware designs. In th is talk performance directed synthesis targeting throughput based computat ions rather than transitional high-level synthesis techniques is proposed based on template-based approaches. With templates\, given data flow graph s are automatically converted into the ones for high performance with FPGA implementation by using SAT-based automatic refinement methods. Then we f urther explore the use of approximate computation to reduce the amount of hardware while keeping the required accuracy. We discuss the proposed tech niques from the viewpoints of a couple of case studies\, such as neural ne twork simulation and HEVC (High Efficiency Video Coding)\n\nCo-sponsored b y: City University of Hong Kong\n\nSpeaker(s): Prof. Masahiro Fujita\, \n\ nBldg: City University of Hong Kong\, G6315\, Green Zone\, AC1\, DEPARTMEN T OF ELECTRONIC ENGINEERING\, Hong Kong\, Guangdong\, China LOCATION:Bldg: City University of Hong Kong\, G6315\, Green Zone\, AC1\, DE PARTMENT OF ELECTRONIC ENGINEERING\, Hong Kong\, Guangdong\, China ORGANIZER:r.cheung@ieee.org SEQUENCE:0 SUMMARY:seminar on Template based high-level and logic synthesis with appro ximate computation for higher and energy efficient computing URL;VALUE=URI:https://events.vtools.ieee.org/m/156195 X-ALT-DESC:Description: <br /><p>Although FPGA or hardware-based implementa tion of software can give us not only higher performance but also energy e fficient computing\, efficient implementation algorithms as hardware and a s software can be significantly different. Typical high-level synthesis me thods may not concentrate on this issue\, as they are targeting general ha rdware designs. In this talk performance directed synthesis targeting thro ughput based computations rather than transitional high-level synthesis te chniques is proposed based on template-based approaches. With templates\, given data flow graphs are automatically converted into the ones for high performance with FPGA implementation by using SAT-based automatic refineme nt methods. Then we further explore the use of approximate computation to reduce the amount of hardware while keeping the required accuracy. We disc uss the proposed techniques from the viewpoints of a couple of case studie s\, such as neural network simulation and HEVC (High Efficiency Video Codi ng)</p> END:VEVENT END:VCALENDAR