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DTSTART:20180325T030000
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DTSTAMP:20181211T113959Z
UID:FEA20F5F-56A3-4AAD-8835-95A9604D65BF
DTSTART;TZID=Europe/Madrid:20180116T100000
DTEND;TZID=Europe/Madrid:20180116T170000
DESCRIPTION:This event is a one-day technical seminar providing a complete 
 overview of Synopsys Analog custom design and verification Platform. Synop
 sys Custom Compiler is a modern Analog Design environment allowing you to 
 drastically reduce your schematic and layout effort.\n\nIn this session we
  will demonstrate how Custom Compiler's visually-assisted automation has t
 ransformed analog layout methodology\, and show you how Custom Compiler's 
 assisted placement\, assisted routing\, and template-based design reuse ca
 pabilities can reduce layout tasks from days to hours. The seminar will al
 so highlight the tight integration with Synopsys Analog Mixed Signal verif
 ication tools (HSpice\, FineSim and CustomSim) Synopsys physical verificat
 ion and parasitic extraction (IC Validator & StarRC) to deliver a “Custo
 m IC design Platform”. A testimonial will also be provided by IMASENIC A
 dvanced Imaging.\n\nWho Should Attend: Engineers and managers who are inte
 rested in Analog and Custom Design.\n\nCo-sponsored by: Institute of Micro
 electronics of Barcelona IMB-CNM\n\nAgenda: \n10:00 a.m. Introduction\n\n1
 0:15 a.m. Synopsys Analog Custom IC flow overview\n\n10:45 a.m. Custom Com
 piler Schematic Edition\, Simulation Environment demo\n\n1:00 p.m. Lunch (
 provided)\n\n2:00 p.m. Layout Edition\, in-design verification & parasitic
  extraction\n\n3:30 p.m. Break\n\n4:00 p.m. Testimonial and Q&A\n\n5:00 p.
 m. Finish\n\nUAB Bellaterra-Campus\, Plaça Cívica\, s/n Bellaterra\, Bar
 celona\, Cataluna\, Spain\,  08193
LOCATION:UAB Bellaterra-Campus\, Plaça Cívica\, s/n Bellaterra\, Barcelon
 a\, Cataluna\, Spain\,  08193
ORGANIZER:Lluis.Teres@csic.es
SEQUENCE:4
SUMMARY:Synopsys Seminar (Barcelona)
URL;VALUE=URI:https://events.vtools.ieee.org/m/157469
X-ALT-DESC:Description: <br /><p>This event is a one-day technical seminar 
 providing a complete overview of Synopsys Analog custom design and verific
 ation Platform. Synopsys Custom Compiler is a modern Analog Design environ
 ment allowing you to drastically reduce your schematic and layout effort.<
 /p>\n<p>In this session we will demonstrate how Custom Compiler's visually
 -assisted automation has transformed analog layout methodology\, and show 
 you how Custom Compiler's assisted placement\, assisted routing\, and temp
 late-based design reuse capabilities can reduce layout tasks from days to 
 hours. The seminar will also highlight the tight integration with Synopsys
  Analog Mixed Signal verification tools (HSpice\, FineSim and CustomSim) S
 ynopsys physical verification and parasitic extraction (IC Validator &amp\
 ; StarRC) to deliver a &ldquo\;Custom IC design Platform&rdquo\;. A testim
 onial will also be provided by IMASENIC Advanced Imaging.</p>\n<p>Who Shou
 ld Attend: Engineers and managers who are interested in Analog and Custom 
 Design.</p><br /><br />Agenda: <br /><p>10:00 a.m.&nbsp\;&nbsp\;&nbsp\;&nb
 sp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\; Introduction</p>\n<p>10:15 
 a.m.&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;
  Synopsys Analog Custom IC flow overview</p>\n<p>10:45 a.m.&nbsp\;&nbsp\;&
 nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\; Custom Compiler Sc
 hematic Edition\, Simulation Environment demo</p>\n<p>1:00 p.m.&nbsp\;&nbs
 p\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\; 
 Lunch (provided)</p>\n<p>2:00 p.m.&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp
 \;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\; Layout Edition\, in-design ve
 rification &amp\; parasitic extraction</p>\n<p>3:30 p.m.&nbsp\;&nbsp\;&nbs
 p\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\; Break</
 p>\n<p>4:00 p.m.&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&n
 bsp\;&nbsp\;&nbsp\;&nbsp\; Testimonial and Q&amp\;A</p>\n<p>5:00 p.m.&nbsp
 \;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&n
 bsp\; Finish</p>
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