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VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
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TZID:Europe/Madrid
BEGIN:DAYLIGHT
DTSTART:20180325T030000
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3
TZNAME:CEST
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BEGIN:STANDARD
DTSTART:20171029T020000
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TZOFFSETTO:+0100
RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10
TZNAME:CET
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BEGIN:VEVENT
DTSTAMP:20180522T111908Z
UID:FB0F01F4-C733-4929-B499-9548D46164F5
DTSTART;TZID=Europe/Madrid:20180308T083000
DTEND;TZID=Europe/Madrid:20180309T123000
DESCRIPTION:This two-day workshop is aimed at researchers and hardware engi
 neers. It covers fast design of digital systems (e.g. FPGA\, ASIC) with th
 e electronic design tool AHIR. AHIR enables the hardware compilation of a 
 circuit description. The input entry is a high‐level programming languag
 e and the output is fully functional VHDL. There will be both theory (day 
 1) and lab (day 2) sessions.\n\nCo-sponsored by: Universidad CEU San Pablo
 \n\nSpeaker(s): Madhav P. Desai\, \n\nAgenda: \n8 March. 8:30h‐12:30h. I
 ntroduction to the AHIR tool suite.\n- Language Aa\n- VHDL generation\n- V
 erification\n\n9 March. 8:30h‐12:30h. Case study: real‐time ECG charac
 terization.\n\nBldg: Escuela Politécnica Superior\, Universidad CEU San P
 ablo\, Campus de Montepríncipe\, Alcorcon\, Madrid\, Spain\, 28925
LOCATION:Bldg: Escuela Politécnica Superior\, Universidad CEU San Pablo\, 
 Campus de Montepríncipe\, Alcorcon\, Madrid\, Spain\, 28925
ORGANIZER:antonio.lopez@ieee.org
SEQUENCE:3
SUMMARY:Workshop on Fast Design of Digital Systems
URL;VALUE=URI:https://events.vtools.ieee.org/m/168394
X-ALT-DESC:Description: &lt;br /&gt;&lt;p&gt;This two-day workshop is aimed at research
 ers and hardware engineers. It covers&amp;nbsp\;fast design of digital systems
  (e.g. FPGA\, ASIC) with the electronic design tool AHIR. AHIR enables the
  hardware compilation of a circuit description. The input entry is a high
 ‐level programming language and the output is fully functional VHDL. The
 re will be both theory (day 1) and lab (day 2) sessions.&lt;/p&gt;&lt;br /&gt;&lt;br /&gt;Ag
 enda: &lt;br /&gt;&lt;p&gt;8 March. 8:30h‐12:30h. Introduction to the AHIR tool suit
 e.&lt;br /&gt;&amp;nbsp\;- Language Aa&lt;br /&gt;&amp;nbsp\;- VHDL generation&lt;br /&gt;&amp;nbsp\;- V
 erification&lt;/p&gt;\n&lt;p&gt;9 March. 8:30h‐12:30h. Case study: real‐time ECG c
 haracterization.&lt;/p&gt;
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