BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:US/Eastern BEGIN:DAYLIGHT DTSTART:20180311T030000 TZOFFSETFROM:-0500 TZOFFSETTO:-0400 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:EDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20181104T010000 TZOFFSETFROM:-0400 TZOFFSETTO:-0500 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:EST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20180503T000000Z UID:48C3E9CC-D204-4FF3-BF42-8278AB4890F9 DTSTART;TZID=US/Eastern:20180329T181000 DTEND;TZID=US/Eastern:20180329T194000 DESCRIPTION:We continue our sequence of in-depth tech events for the year w ith a talk on test methods for electronic devices\n\nFrom multi-core chips in slim smartphone devices or compact packaging of power semiconductor mo dules for lightweight electric vehicle inverters\, understanding semicondu ctor package heat dissipation remains important for performance and produc t reliability purposes.\n\nThis presentation introduces electrical test me thods covered by JEDEC 51-1 standards. By utilizing this approach\, the di fficulties and problems measuring temperature at the component’s die are overcome. Further use of the techniques allow transient thermal response measurement\, for package and system thermal characterization\, which can be applied to identifying thermal degradation\, verifying package material quality for manufacturing purposes\, and supporting thermal design proces ses by generating validated semiconductor package thermal models. This met hod is an alternative to XRay\, CSAM or destructive inspection methods for certain failure diagnosis applications.\n\nKey topics:\n\n- Electrical te st methods for thermal measurement\, JEDEC 51-1 series\, transient thermal response & structure functions\n\n- Package material structure object map ping\n\n- Power Electronics – IGBT thermal degradation identification & power cycling studies\n\n- Package Material Defect Identification\n\n- Rec ent IP developments in detailed thermal model calibration\n\nFollowing thi s there will a general discussion\, Q&A and update on the current state of landscape (recent major annoucenments will be also shared)\n\nCo-sponsore d by: Prof. Subramaniam Ganesan & Education Society SE Michigan chapter\n\ nSpeaker(s): Joe Proulx\, \n\nAgenda: \n6:00 PM - Welcome and Introduction s\, Chapter business update\, Pizza\n\n6:15 PM - Main Presentation: Utiliz ing Electrical Test Methods for Thermal Measurement\, Reliability and Qual ity Assessment\n\n7:30 PM - Post event discussion\, Q&A and landscape upda te\n\n7:45 PM - Wrap Up\n\n7:45 to 8 PM - Networking\n\nProfessional Devel opment Hours/Units (PDU/PDH) are available for this talk\, but must be req uested in advance!\n\nRoom: EC 254\, Bldg: Engineering Center\, 115 Librar y Drive\, Oakland University\, Rochester\, Michigan\, United States\, 4830 9-4479 LOCATION:Room: EC 254\, Bldg: Engineering Center\, 115 Library Drive\, Oakl and University\, Rochester\, Michigan\, United States\, 48309-4479 ORGANIZER:sharan.kalwani@ieee.org SEQUENCE:9 SUMMARY:Utilizing Electrical Test Methods for Thermal Measurement\, Reliabi lity and Quality Assessment URL;VALUE=URI:https://events.vtools.ieee.org/m/169382 X-ALT-DESC:Description: <br /><p>We continue our sequence of in-depth tech events for the year with a talk on test methods for electronic devices</p> \n<p style="font-weight: 400\;">From multi-core chips in slim smartphone d evices or compact packaging of power semiconductor modules for lightweight electric vehicle inverters\, understanding semiconductor package heat dis sipation remains important for performance and product reliability purpose s.</p>\n<p style="font-weight: 400\;">This presentation introduces electri cal test methods covered by JEDEC 51-1 standards.&nbsp\; By utilizing this approach\, the difficulties and problems measuring temperature at the com ponent&rsquo\;s die are overcome.&nbsp\; Further use of the techniques all ow transient thermal response measurement\, for package and system thermal characterization\,&nbsp\;which can be applied to identifying thermal degr adation\, verifying package material quality for manufacturing purposes\, and supporting thermal design processes by generating validated semiconduc tor package thermal models. This method is an alternative to XRay\, CSAM o r destructive inspection methods for certain failure diagnosis application s.</p>\n<p style="font-weight: 400\;">Key topics:</p>\n<p style="font-weig ht: 400\;">-&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\ ;&nbsp\;Electrical test methods for thermal measurement\, JEDEC 51-1 serie s\, transient thermal response &amp\; structure functions</p>\n<p style="f ont-weight: 400\;">-&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp \;&nbsp\;&nbsp\;Package material structure object mapping</p>\n<p style="f ont-weight: 400\;">-&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp \;&nbsp\;&nbsp\;Power Electronics &ndash\; IGBT thermal degradation identi fication &amp\; power cycling studies</p>\n<p style="font-weight: 400\;">- &nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;Pack age Material Defect Identification</p>\n<p style="font-weight: 400\;">-&nb sp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;Recent IP developments in detailed thermal model calibration</p>\n<p>Following th is there will a general discussion\, Q&amp\;A and update on the current st ate of landscape (recent major annoucenments will be also shared)</p>\n<p> &nbsp\;</p><br /><br />Agenda: <br /><p><span style="font-family: 'courier new'\, courier\, monospace\; font-size: 12pt\;">6:00 PM - Welcome and Int roductions\, Chapter business update\, Pizza<br /></span></p>\n<p><span st yle="font-family: 'courier new'\, courier\, monospace\; font-size: 12pt\;" >6:15 PM - Main Presentation: Utilizing Electrical Test Methods for Therma l Measurement\, Reliability and Quality Assessment<br /></span></p>\n<p><s pan style="font-family: 'courier new'\, courier\, monospace\; font-size: 1 2pt\;">7:30 PM - Post event discussion\, Q&amp\;A and landscape update <br /></span></p>\n<p><span style="font-family: 'courier new'\, courier\, mon ospace\; font-size: 12pt\;">7:45 PM - Wrap Up</span></p>\n<p><span style=" font-family: 'courier new'\, courier\, monospace\; font-size: 12pt\;">7:45 to 8 PM - Networking&nbsp\;</span></p>\n<p><span style="font-size: 14pt\; "><span style="font-family: 'andale mono'\, monospace\;"><span style="font -size: 10pt\;">Professional Development Hours/Units (PDU/PDH) are availabl e for this talk\, but must be requested in advance!</span></span></span></ p> END:VEVENT END:VCALENDAR