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DTSTAMP:20180523T183547Z
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DTSTART;TZID=US/Pacific:20180522T183000
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DESCRIPTION:Verilog is the accepted language of choice for modeling and sim
 ulating digital designs. For analog blocks the tool choice is a low level 
 circuit simulator like HSPICE or Spectre. For PLL’s a common misconcepti
 on is that you can use Verilog to model a PLL if you don't care about accu
 racy\, but if you do care about precision\, you'll need an analog circuit 
 simulator like HSPICE or Spectre. Various options like Verilog-A and Veril
 og-AMS are attempts to achieve the best of both worlds\, but in this talk\
 , we propose that the tool of choice for modeling and studying PLL’s and
  is plain “digital” Verilog. It's the right tool\, but almost always u
 sed the wrong way for modeling PLL's. Understanding how the underlying sim
 ulation engine in Verilog works enables us to set up our models in a very 
 precise\, yet very simple manner. The efficiency and speed of Verilog allo
 ws us to literally watch our PLL designs come alive in the time domain wit
 h timing accuracy that can't be achieved in an analog circuit simulator. W
 atching designs operate in the time domain crystalizes our understanding o
 f them\, and enables us to study and quantify transient and other non-line
 ar phenomena.\n\nCo-sponsored by: Cristian Cismaru\n\nSpeaker(s): Greg War
 war\, \n\nAgenda: \n6:30-7:00pm Gather and Pizza/Refreshments\n\n7:00-8:00
 pm Presentation\n\nBldg: 889\, Skyworks Solutions\, Inc.\, 649 Lawrence Dr
 ive\, Newbury Park\, California\, United States\, 91320
LOCATION:Bldg: 889\, Skyworks Solutions\, Inc.\, 649 Lawrence Drive\, Newbu
 ry Park\, California\, United States\, 91320
ORGANIZER:ccismaru@ieee.org
SEQUENCE:4
SUMMARY:PLL's and Phase Noise Modeling in Verilog
URL;VALUE=URI:https://events.vtools.ieee.org/m/172159
X-ALT-DESC:Description: <br /><p>Verilog is the accepted language of choice
  for modeling and simulating digital designs. For analog blocks the tool c
 hoice is a low level circuit simulator like HSPICE or Spectre. For PLL&rsq
 uo\;s a common misconception is that you can use Verilog to model a PLL if
  you don't care about accuracy\, but if you do care about precision\, you'
 ll need an analog circuit simulator like HSPICE or Spectre. Various option
 s like Verilog-A and Verilog-AMS are attempts to achieve the best of both 
 worlds\, but in this talk\, we propose that the tool of choice for modelin
 g and studying PLL&rsquo\;s and is plain &ldquo\;digital&rdquo\; Verilog. 
 It's the right tool\, but almost always used the wrong way for modeling PL
 L's. Understanding how the underlying simulation engine in Verilog works e
 nables us to set up our models in a very precise\, yet very simple manner.
  The efficiency and speed of Verilog allows us to literally watch our PLL 
 designs come alive in the time domain with timing accuracy that can't be a
 chieved in an analog circuit simulator. Watching designs operate in the ti
 me domain crystalizes our understanding of them\, and enables us to study 
 and quantify transient and other non-linear phenomena.</p><br /><br />Agen
 da: <br /><p>6:30-7:00pm Gather and Pizza/Refreshments</p>\n<p>&nbsp\;</p>
 \n<p>7:00-8:00pm Presentation</p>\n<p>&nbsp\;</p>
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