BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Canada/Pacific BEGIN:DAYLIGHT DTSTART:20180311T030000 TZOFFSETFROM:-0800 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:PDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20181104T010000 TZOFFSETFROM:-0700 TZOFFSETTO:-0800 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:PST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20200716T002623Z UID:38FBBEE0-C196-46E5-A1CB-03C28B9FB91B DTSTART;TZID=Canada/Pacific:20180518T110000 DTEND;TZID=Canada/Pacific:20180518T120000 DESCRIPTION:IEEE Electron Device Society Distinguished Lecture\n\nTitle: Na nocarbon Interconnects\n\nSpeaker: Dr. Cary Yang\, Professor\, Center for Nanostructures\, Santa Clara University\n\nDate: May 18th (Friday)\, 2018\ n\nTime: 11 am-12pm\n\nLocation: ASB 10900\, Presentation Studio\, Applied Science Building\, SFU\, 8888 University Dr.\, Burnaby\, BC\n\nREFRESHMEN TS WILL BE PROVIDED.\n\nAbstract: Continuous downward scaling in silicon i ntegrated circuit technology into the sub‐20 nm regime has created criti cal challenges in chip manufacturing\, among them\, reliability and perfor mance of on‐chip interconnects. Current interconnect materials\, Cu and W\, face increased reliability challenges in the nanoscale as a result of electromigration failures at high current densities. Materials such as nan ocarbons\, metal silicides\, and metallic nanowires are being considered a s potential replacements for Cu and W. In particular\, due to its superior electrical and mechanical properties as well as much higher current‐car rying capacities\, carbon nanotube (CNT) is a serious contender to replace Cu and W in on‐chip interconnect via. However\, the main challenge to f unctionalizing CNT vias is the metal‐CNT contact resistance. To mitigate such challenge\, a seamless three‐dimensional all‐carbon interconnect structure has been fabricated by growing CNTs directly on one or few laye rs of graphene (MLG). This 3D structure can potentially yield low resistan ce due to the strong C‐C sp2 bonding in CNT and graphene and across the CNT‐graphene interface. While such growth has been demonstrated\, the CN T/graphene interfacial nanostructure and how it impacts the electrical pro perties of the 3D structure are far from being understood.\n\nOur test str ucture consists of MLG grown by annealing a Ni thin film in H2/CH4 ambient inside a low‐pressure PECVD chamber\, before being transferred onto an oxide‐covered silicon substrate. Vertically aligned CNTs are then grown on the transferred MLG in a PECVD system using a similar recipe as in our previous work on CNT vias\, resulting in a 3D all‐carbon interconnect st ructure. Scanning and transmission electron microscopy images reveal CNT a lignment and interfacial nanostructure comparable to the CNT‐Cr interfac e in CNT via. The measured resistance of the 3D structure is compared with those of sub‐100 nm linewidth CNT vias. Our results demonstrate e the f easibility of fabricating a 3D CNT/graphene device\, which can serve as th e building block for all‐carbon interconnects. Enhanced understanding of the relationship between interfacial nanostructure and device resistance can lead to eventual functionalization of contacts between CNT vias and a graphene‐based planar interconnect network in the most advanced technolo gy nodes.\n\nBiography: Cary Y. Yang received the B.S.\, M.S.\, and Ph.D. degrees in electrical engineering from the University of Pennsylvania. Aft er working at M.I.T.\, NASA Ames Research Center\, and Stanford University on electronic properties of nanostructure surfaces and interfaces\, he fo unded Surface Analytic Research\, a Silicon Valley company focusing on spo nsored research projects covering various applications of surfaces and nan ostructures. He joined Santa Clara University in 1983 and is currently Pro fessor of Electrical Engineering and Director of TENT Laboratory\, a SCU f acility located inside NASA Ames. He was the Founding Director of Microele ctronics Laboratory and Center for Nanostructures\, and served as Chair of Electrical Engineering and\n\nAssociate Dean of Engineering at Santa Clar a. His research spans from silicon‐based nanoelectronics to nanostructur e interfaces in electronic\, biological\, and energy‐storage systems. An IEEE Life Fellow\, he served as Editor of the IEEE Transactions on Electr on Devices\, President of the IEEE Electron Devices Society\, and elected member of the IEEE Board of Directors. He was appointed Vice Chair of the IEEE Awards Board in 2013 and 2014. He received the 2004 IEEE Educational Activities Board Meritorious Achievement Award in Continuing Education "fo r extensive and innovative contributions to the continuing education of wo rking professionals in the field of micro/nanoelectronics\," and the IEEE Electron Devices Society Distinguished Service Award in 2005. From 2008 to 2013\, he held the Bao Yugang Chair Professorship at Zhejiang University in China.\n\nSpeaker(s): Dr. Cary Yang\, \n\nRoom: ASB 10900\, Bldg: Appli ed Science Building\, 8888 University Dr.\, Burnaby\, British Columbia\, C anada\, V5A1S6 LOCATION:Room: ASB 10900\, Bldg: Applied Science Building\, 8888 University Dr.\, Burnaby\, British Columbia\, Canada\, V5A1S6 ORGANIZER:mmadachi@sfu.ca SEQUENCE:2 SUMMARY:IEEE Electron Device Society Distinguished Lecture by Dr. Cary Yang \, Santa Clara University URL;VALUE=URI:https://events.vtools.ieee.org/m/173084 X-ALT-DESC:Description: <br /><p>IEEE Electron Device Society Distinguished Lecture</p>\n<p>Title: Nanocarbon Interconnects</p>\n<p>Speaker: Dr. Cary Yang\, Professor\, Center for Nanostructures\, Santa Clara University</p> \n<p>Date: May 18<sup>th</sup> (Friday)\, 2018</p>\n<p>Time: 11 am-12pm</p >\n<p>Location: ASB 10900\, Presentation Studio\, Applied Science Building \, SFU\, 8888 University Dr.\, Burnaby\, BC</p>\n<p>REFRESHMENTS WILL BE P ROVIDED.</p>\n<p>Abstract: Continuous downward scaling in silicon integrat ed circuit technology into the sub‐20 nm regime has created critical cha llenges in chip manufacturing\, among them\, reliability and performance o f on‐chip interconnects. Current interconnect materials\, Cu and W\, fac e increased reliability challenges in the nanoscale as a result of electro migration failures at high current densities. Materials such as nanocarbon s\, metal silicides\, and metallic nanowires are being considered as poten tial replacements for Cu and W. In particular\, due to its superior electr ical and mechanical properties as well as much higher current‐carrying c apacities\, carbon nanotube (CNT) is a serious contender to replace Cu and W in on‐chip interconnect via. However\, the main challenge to function alizing CNT vias is the metal‐CNT contact resistance. To mitigate such c hallenge\, a seamless three‐dimensional all‐carbon interconnect struct ure has been fabricated by growing CNTs directly on one or few layers of g raphene (MLG). This 3D structure can potentially yield low resistance due to the strong C‐C sp2 bonding in CNT and graphene and across the CNT‐g raphene interface. While such growth has been demonstrated\, the CNT/graph ene interfacial nanostructure and how it impacts the electrical properties of the 3D structure are far from being understood.</p>\n<p>Our test struc ture consists of MLG grown by annealing a Ni thin film in H2/CH4 ambient i nside a low‐pressure PECVD chamber\, before being transferred onto an ox ide‐covered silicon substrate. Vertically aligned CNTs are then grown on the transferred MLG in a PECVD system using a similar recipe as in our pr evious work on CNT vias\, resulting in a 3D all‐carbon interconnect stru cture. Scanning and transmission electron microscopy images reveal CNT ali gnment and interfacial nanostructure comparable to the CNT‐Cr interface in CNT via. The measured resistance of the 3D structure is compared with t hose of sub‐100 nm linewidth CNT vias. Our results demonstrate e the fea sibility of fabricating a 3D CNT/graphene device\, which can serve as the building block for all‐carbon interconnects. Enhanced understanding of t he relationship between interfacial nanostructure and device resistance ca n lead to eventual functionalization of contacts between CNT vias and a gr aphene‐based planar interconnect network in the most advanced technology nodes.</p>\n<p>Biography: Cary Y. Yang received the B.S.\, M.S.\, and Ph. D. degrees in electrical engineering from the University of Pennsylvania. After working at M.I.T.\, NASA Ames Research Center\, and Stanford Univers ity on electronic properties of nanostructure surfaces and interfaces\, he founded Surface Analytic Research\, a Silicon Valley company focusing on sponsored research projects covering various applications of surfaces and nanostructures. He joined Santa Clara University in 1983 and is currently Professor of Electrical Engineering and Director of TENT Laboratory\, a SC U facility located inside NASA Ames. He was the Founding Director of Micro electronics Laboratory and Center for Nanostructures\, and served as Chair of Electrical Engineering and</p>\n<p>Associate Dean of Engineering at Sa nta Clara. His research spans from silicon‐based nanoelectronics to nano structure interfaces in electronic\, biological\, and energy‐storage sys tems. An IEEE Life Fellow\, he served as Editor of the IEEE Transactions o n Electron Devices\, President of the IEEE Electron Devices Society\, and elected member of the IEEE Board of Directors. He was appointed Vice Chair of the IEEE Awards Board in 2013 and 2014. He received the 2004 IEEE Educ ational Activities Board Meritorious Achievement Award in Continuing Educa tion "for extensive and innovative contributions to the continuing educati on of working professionals in the field of micro/nanoelectronics\," and t he IEEE Electron Devices Society Distinguished Service Award in 2005. From 2008 to 2013\, he held the Bao Yugang Chair Professorship at Zhejiang Uni versity in China.</p> END:VEVENT END:VCALENDAR