BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:US/Eastern BEGIN:DAYLIGHT DTSTART:20190310T030000 TZOFFSETFROM:-0500 TZOFFSETTO:-0400 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:EDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20181104T010000 TZOFFSETFROM:-0400 TZOFFSETTO:-0500 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:EST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20181109T214500Z UID:EEAC8879-5F6A-422C-8E73-5412B185856E DTSTART;TZID=US/Eastern:20181109T110000 DTEND;TZID=US/Eastern:20181109T123000 DESCRIPTION:The presentation is sponsored by:\n\nIEEE Rochester Section: Co mputer and Computational Intelligence Societies Joint Chapter\n\nand RIT's GCCIS PhD Colloquium.\n\nAbstract:\n\nIt is found that existing and power ful cache side-channel attacks on Intel\narchitectures\, including Prime+P robe\, are ineffective on mobile and\nInternet-of-things (IoT) devices pow ered by ARM architectures. The trust in\nARM's hardware-isolated execution environments\, namely TrustZone\, was also\nreinforced by these findings. However\, those discoveries do not rule out novel\nand more sophisticated cache side-channel attacks that leverage overlooked\nhardware features. I n this talk\, I will present a novel Prime+Count attack\nthat can be used to build reliable covert channels between the normal and\nsecure world of TrustZone\, which breaks one of its fundamental security\nguarantees.\n\nO n the other hand\, protections that can defeat previous cache side-channel \nattacks on Intel architectures are not necessarily effective in mitigati ng\nnovel cache attacks on ARM platforms. Such solutions attempt to mitiga te\nattacks by explicitly or implicitly creating a private space\, in whic h\nconstant-time access to sensitive data is assured. However\, some of th e\nattempts utilize hardware features available only on certain Intel proc essors.\nIn this talk\, I will also discuss a defense against cache side-c hannel attacks\nthat can protect against both dedicated cache (L1) and sha red cache (L2)\nattacks on mobile and IoT devices.\n\nCo-sponsored by: RIT 's GCCIS PhD Colloquium\n\nSpeaker(s): Ziming Zhao\, \n\nAgenda: \n11:00am -- presentation\n\n12:00pm -- pizza / networking\n\nNote: no advance regi stration required\n\nRIT visitor parking suggestions:\n\n1) Stop at the we lcome center and obtain visitor parking permit -- [[Google map](https://go o.gl/maps/KzoCpa2kdF82)]\n\n2) Then park at Visitor Parking in the J-lot - - [[Google map](https://goo.gl/maps/5xUSPr3189L2)]\n\n(11/6/18 addition) V isitor's Parking:\n\nVisitors may park in Lots G or H using this event per mit: http://ewh.ieee.org/r1/rochester/computer/2018/20181109/RIT.ParkingPe rmit.11-9-18.IEEE.pdf\n\nAdditional Links:\n\nIEEE meeting entry : https:/ /events.vtools.ieee.org/m/176639\n\nCS/CIS website / venue info: http://ew h.ieee.org/r1/rochester/computer/\n\nflyer (printable): http://ewh.ieee.or g/r1/rochester/computer/2018/20181109/Zhao.20181109.pdf\n\nRoom: 3560\, Bl dg: Golisano Hall - Bldg 70\, RIT\, 152 Lomb Memorial Dr. \, Rochester\, N ew York\, United States\, 14623 LOCATION:Room: 3560\, Bldg: Golisano Hall - Bldg 70\, RIT\, 152 Lomb Memori al Dr. \, Rochester\, New York\, United States\, 14623 ORGANIZER:bo.yuan@rit.edu SEQUENCE:13 SUMMARY:CS/CIS Event: Cache Side-Channel Attack and Defense on Mobile and I oT Devices URL;VALUE=URI:https://events.vtools.ieee.org/m/176639 X-ALT-DESC:Description: <br /><div style="margin: 15px\;">\n<div style="wid th: 780px\; background-color: #fff\; padding: 0px\;">\n<p>The presentation is sponsored by:</p>\n<p>&nbsp\;&nbsp\;&nbsp\; <strong>IEEE Rochester Sec tion:&nbsp\;</strong><strong>Computer and Computational Intelligence Socie ties</strong><strong> Joint Chapter</strong></p>\n<p>&nbsp\;&nbsp\;&nbsp\; and <strong>RIT's GCCIS PhD Colloquium.<br /></strong></p>\n<p>&nbsp\;</p >\n<p><strong><span style="text-decoration: underline\;">Abstract:</span>< /strong></p>\n</div>\n</div>\n<p>It is found that existing and powerful ca che side-channel attacks on Intel <br />architectures\, including Prime+Pr obe\, are ineffective on mobile and <br />Internet-of-things (IoT) devices powered by ARM architectures. The trust in <br />ARM's hardware-isolated execution environments\, namely TrustZone\, was also <br />reinforced by t hese findings. However\, those discoveries do not rule out novel <br />and more sophisticated cache side-channel attacks that leverage overlooked <b r />hardware features. In this talk\, I will present a novel Prime+Count a ttack <br />that can be used to build reliable covert channels between the normal and <br />secure world of TrustZone\, which breaks one of its fund amental security <br />guarantees.</p>\n<p>On the other hand\, protections that can defeat previous cache side-channel <br />attacks on Intel archit ectures are not necessarily effective in mitigating <br />novel cache atta cks on ARM platforms. Such solutions attempt to mitigate <br />attacks by explicitly or implicitly creating a private space\, in which <br />constan t-time access to sensitive data is assured. However\, some of the <br />at tempts utilize hardware features available only on certain Intel processor s. <br />In this talk\, I will also discuss a defense against cache side-c hannel attacks <br />that can protect against both dedicated cache (L1) an d shared cache (L2) <br />attacks on mobile and IoT devices.</p><br /><br />Agenda: <br /><p>11:00am -- presentation</p>\n<p>12:00pm -- pizza / netw orking</p>\n<p>Note: no advance registration required</p>\n<p><strong>RIT visitor parking suggestions:</strong></p>\n<p>&nbsp\;&nbsp\;&nbsp\; 1) Sto p at the welcome center and obtain visitor parking permit -- [<a href="htt ps://goo.gl/maps/KzoCpa2kdF82" target="_blank" rel="noopener">Google map</ a>]</p>\n<p>&nbsp\;&nbsp\;&nbsp\; 2) Then park at Visitor Parking in the J -lot -- [<a href="https://goo.gl/maps/5xUSPr3189L2" target="_blank" rel="n oopener">Google map</a>]</p>\n<p><strong>(11/6/18 addition) Visitor's Park ing:</strong></p>\n<p><strong>&nbsp\;&nbsp\;&nbsp\;&nbsp\; </strong>Visito rs may park in Lots G or H using this event permit: <a href="http://ewh.ie ee.org/r1/rochester/computer/2018/20181109/RIT.ParkingPermit.11-9-18.IEEE. pdf" target="_blank" rel="noopener">http://ewh.ieee.org/r1/rochester/compu ter/2018/20181109/RIT.ParkingPermit.11-9-18.IEEE.pdf</a></p>\n<p><strong>A dditional Links:</strong></p>\n<p style="font-size: 11px\; font-family: Ve rdana\,Arial\,Helvetica\,sans-serif\; color: #000000\;">&nbsp\;&nbsp\;&nbs p\;<strong>&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\; IEEE meeting entry :</stron g>&nbsp\;<a title="IEEE vtools entry" href="https://events.vtools.ieee.org /m/176639" target="_blank" rel="noopener">https://events.vtools.ieee.org/m /176639</a></p>\n<div style="margin: 15px\;">\n<div style="width: 780px\; background-color: #fff\; padding: 0px\;">\n<div style="margin: 15px\;">\n< div style="width: 780px\; background-color: #fff\; padding: 0px\;">\n<p st yle="font-size: 11px\; font-family: Verdana\,Arial\,Helvetica\,sans-serif\ ; color: #000000\;">&nbsp\; <strong>CS/CIS website / venue info:&nbsp\;&nb sp\; </strong><a href="http://ewh.ieee.org/r1/rochester/computer/" target= "_blank" rel="noopener">http://ewh.ieee.org/r1/rochester/computer/</a></p> \n<p style="font-size: 11px\; font-family: Verdana\,Arial\,Helvetica\,sans -serif\; color: #000000\;"><strong>&nbsp\;&nbsp\; flyer (printable):</stro ng> <a href="http://ewh.ieee.org/r1/rochester/computer/2018/20181109/Zhao. 20181109.pdf" target="_blank" rel="noopener">http://ewh.ieee.org/r1/roches ter/computer/2018/20181109/Zhao.20181109.pdf</a></p>\n</div>\n</div>\n</di v>\n</div>\n<p>&nbsp\;</p> END:VEVENT END:VCALENDAR