BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Europe/Warsaw BEGIN:DAYLIGHT DTSTART:20180325T030000 TZOFFSETFROM:+0100 TZOFFSETTO:+0200 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3 TZNAME:CEST END:DAYLIGHT BEGIN:STANDARD DTSTART:20181028T020000 TZOFFSETFROM:+0200 TZOFFSETTO:+0100 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10 TZNAME:CET END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20181025T141024Z UID:3C8A3297-B8E7-45E9-856F-417DD060F3B1 DTSTART;TZID=Europe/Warsaw:20181017T153000 DTEND;TZID=Europe/Warsaw:20181017T183000 DESCRIPTION:The past several years has seen proliferation of all-digital ph ase-locked loops (ADPLL) for RF and high-performance frequency synthesis d ue to their clear benefits of flexibility\, reconfigurability\, transfer f unction precision\, settling speed\, frequency modulation capability\, and amenability to integration with digital baseband and application processo rs. When implemented in nanoscale CMOS\, the ADPLL also exhibits advantage s of better performance\, lower power consumption\, lower area and cost ov er the traditional analog-intensive charge-pump PLL. In a typical ADPLL\, a traditional VCO got directly replaced by a digitally controlled oscillat or (DCO) for generating an output variable clock\, a traditional phase/fre quency detector and a charge pump got replaced by a time-to-digital conver ter (TDC) for detecting phase departures of the variable clock\nversus the frequency reference (FREF) clock\, and an analog loop RC filter got repla ced with a digital loop filter. The conversion gains of the DCO and TDC ci rcuits are readily estimated and compensated using ”free” but powerful digital logic.\n\nBldg: B1\, AGH University of Science and Technology\, C racow\, Malopolskie\, Poland\, 30-059 LOCATION:Bldg: B1\, AGH University of Science and Technology\, Cracow\, Mal opolskie\, Poland\, 30-059 ORGANIZER:kasinski@agh.edu.pl SEQUENCE:1 SUMMARY:All-Digital Phase-Locked Loop (ADPLL) by Prof. Robert Bogdan Stasze wski URL;VALUE=URI:https://events.vtools.ieee.org/m/179204 X-ALT-DESC:Description: <br /><p>The past several years has seen proliferat ion of all-digital phase-locked loops (ADPLL) for RF and high-performance frequency synthesis due to their clear benefits of flexibility\, reconfigu rability\, transfer function precision\, settling speed\, frequency modula tion capability\, and amenability to integration with digital baseband and application processors. When implemented in nanoscale CMOS\, the ADPLL al so exhibits advantages of better performance\, lower power consumption\, l ower area and cost over the traditional analog-intensive charge-pump PLL. In a typical ADPLL\, a traditional VCO got directly replaced by a digitall y controlled oscillator (DCO) for generating an output variable clock\, a traditional phase/frequency detector and a charge pump got replaced by a t ime-to-digital converter (TDC) for detecting phase departures of the varia ble clock<br />versus the frequency reference (FREF) clock\, and an analog loop RC filter got replaced with a digital loop filter. The conversion ga ins of the DCO and TDC circuits are readily estimated and compensated usin g &rdquo\;free&rdquo\; but powerful digital logic.</p> END:VEVENT END:VCALENDAR