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VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
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TZID:Poland
BEGIN:DAYLIGHT
DTSTART:20190331T030000
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DTSTART:20181028T020000
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BEGIN:VEVENT
DTSTAMP:20190115T102625Z
UID:4DCE597C-F922-4BFF-8BFA-89ABC9C33091
DTSTART;TZID=Poland:20181220T153000
DTEND;TZID=Poland:20181220T180000
DESCRIPTION:The past several years has seen proliferation of all-digital ph
 ase-locked loops (ADPLL) for RF and high-performance frequency synthesis d
 ue to their clear benefits of flexibility\, reconfigurability\, transfer f
 unction precision\, settling speed\, frequency modulation capability\, and
  amenability to integration with digital baseband and application processo
 rs. When implemented in nanoscale CMOS\, the ADPLL also exhibits advantage
 s of better performance\, lower power consumption\, lower area and cost ov
 er the traditional analog-intensive charge-pump PLL. In a typical ADPLL\, 
 a traditional VCO got directly replaced by a digitally controlled oscillat
 or (DCO) for generating an output variable clock\, a traditional phase/fre
 quency detector and a charge pump got replaced by a time-to-digital conver
 ter (TDC) for detecting phase departures of the variable clock\nversus the
  frequency reference (FREF) clock\, and an analog loop RC filter got repla
 ced with a digital loop filter. The conversion gains of the DCO and TDC ci
 rcuits are readily estimated and compensated using ”free” but powerful
  digital logic.\n\nThis lecture covers topics related to the Time-to-Digit
 al Converter design.\n\nRoom: 121\, Bldg: B1\, AGH University of Science a
 nd Technology\, Av. Mickiewicza 30\, Cracow\, Malopolskie\, Poland\, 30-05
 9
LOCATION:Room: 121\, Bldg: B1\, AGH University of Science and Technology\, 
 Av. Mickiewicza 30\, Cracow\, Malopolskie\, Poland\, 30-059
ORGANIZER:kasinski@agh.edu.pl
SEQUENCE:1
SUMMARY:LECTURE ON TDCs FOR ADPLL (ALL-DIGITAL PLL) BY PROF. BOGDAN STASZEW
 SKI
URL;VALUE=URI:https://events.vtools.ieee.org/m/184625
X-ALT-DESC:Description: <br /><p>The past several years has seen proliferat
 ion of all-digital phase-locked loops (ADPLL) for RF and high-performance 
 frequency synthesis due to their clear benefits of flexibility\, reconfigu
 rability\, transfer function precision\, settling speed\, frequency modula
 tion capability\, and amenability to integration with digital baseband and
  application processors. When implemented in nanoscale CMOS\, the ADPLL al
 so exhibits advantages of better performance\, lower power consumption\, l
 ower area and cost over the traditional analog-intensive charge-pump PLL. 
 In a typical ADPLL\, a traditional VCO got directly replaced by a digitall
 y controlled oscillator (DCO) for generating an output variable clock\, a 
 traditional phase/frequency detector and a charge pump got replaced by a t
 ime-to-digital converter (TDC) for detecting phase departures of the varia
 ble clock<br />versus the frequency reference (FREF) clock\, and an analog
  loop RC filter got replaced with a digital loop filter. The conversion ga
 ins of the DCO and TDC circuits are readily estimated and compensated usin
 g &rdquo\;free&rdquo\; but powerful digital logic.</p>\n<p>This lecture co
 vers topics related to the Time-to-Digital Converter design.</p>
END:VEVENT
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