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PRODID:IEEE vTools.Events//EN
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TZID:Europe/Madrid
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DTSTART:20190331T030000
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TZOFFSETTO:+0200
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BEGIN:STANDARD
DTSTART:20181028T020000
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BEGIN:VEVENT
DTSTAMP:20190425T074545Z
UID:FD4E43E7-303C-4B5A-BAF7-E24237C33171
DTSTART;TZID=Europe/Madrid:20190220T100000
DTEND;TZID=Europe/Madrid:20190221T133000
DESCRIPTION:The Workshop on Fast Design of Digital Systems is a two-day eve
 nt aimed at researchers and hardware engineers and covers the fast design 
 of digital systems (e.g. FPGA\, ASIC) with the electronic design tool AHIR
 . AHIR enables the hardware compilation of a circuit description. The inpu
 t entry is a high-level programming language and the output is fully funct
 ional VHDL. All sessions are composed of theory and practice. Examples wil
 l be tested on FPGA boards. In day 1 there will be an overview on the late
 st FPGA trends provided by AVNET-Silica Engineers. This is the second edit
 ion of the Workshop\, the first one took place in 2018.\n\nCo-sponsored by
 : Universidad CEU San Pablo\n\nAgenda: \n20 February\n\n10:00-10:15 h: Wel
 come message (Gabriel Caffarena\, USP-CEU)\n\n10:15-11:00 h: New trends in
  FPGA and configurable Soc design (Ricardo Gómez Galarza\, AVNET-Silica)\
 n\n11:00-11:15 h: Coffee break\n\n11:15-13:30h: Lab session I: Introductio
 n to AHIR toolchain (Madhav P. Desai\, IIT-Bombay)\n\n21 February\n\n9:30-
 11:00h: Lab session II: More on AHIR toolchain (Madhav P. Desai\, IIT-Bomb
 ay)\n\n11:00-11:15h: Coffee break\n\n11:15-13:30h: Lab session III: Signal
  processing case study (Madhav P. Desai\, IIT-Bombay)\n\nBldg: Escuela Pol
 itécnica Superior\, Universidad San Pablo CEU\, Campus de Montepríncipe\
 , Alcorcon\, Madrid\, Spain\, 28668
LOCATION:Bldg: Escuela Politécnica Superior\, Universidad San Pablo CEU\, 
 Campus de Montepríncipe\, Alcorcon\, Madrid\, Spain\, 28668
ORGANIZER:antonio.lopez@unavarra.es
SEQUENCE:2
SUMMARY:2nd Workshop on Fast Design of Digital Systems
URL;VALUE=URI:https://events.vtools.ieee.org/m/189107
X-ALT-DESC:Description: <br /><p>The Workshop on Fast Design of Digital Sys
 tems is a two-day event&nbsp\;aimed at <strong>researchers</strong> and <s
 trong>hardware engineers</strong> and covers the fast design of digital sy
 stems (e.g. FPGA\, ASIC) with the electronic design tool AHIR. AHIR enable
 s the hardware compilation of a circuit description. The input entry is a 
 high-level programming language and the output is fully functional VHDL. A
 ll sessions are composed of theory and practice. Examples will be tested o
 n FPGA boards. In day 1 there will be an overview on the latest FPGA trend
 s provided by AVNET-Silica Engineers. This is the second edition of the Wo
 rkshop\, the first one took place in 2018.</p><br /><br />Agenda: <br /><p
 ><strong>20 February</strong></p>\n<p>10:00-10:15 h: Welcome message (Gabr
 iel Caffarena\, USP-CEU)</p>\n<p>10:15-11:00 h: New trends in FPGA and con
 figurable Soc design (Ricardo G&oacute\;mez Galarza\, AVNET-Silica)</p>\n<
 p>11:00-11:15 h: Coffee break</p>\n<p>11:15-13:30h: Lab session I: Introdu
 ction to AHIR toolchain (Madhav P. Desai\, IIT-Bombay)</p>\n<p>&nbsp\;</p>
 \n<p><strong>21 February</strong></p>\n<p>&nbsp\;9:30-11:00h: Lab session 
 II: More on AHIR toolchain &nbsp\;(Madhav P. Desai\, IIT-Bombay)</p>\n<p>&
 nbsp\;11:00-11:15h: Coffee break</p>\n<p>&nbsp\;11:15-13:30h: Lab session 
 III: Signal processing case study (Madhav P. Desai\, IIT-Bombay)</p>
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