BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:CET
BEGIN:DAYLIGHT
DTSTART:20180325T030000
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3
TZNAME:CEST
END:DAYLIGHT
BEGIN:STANDARD
DTSTART:20181028T020000
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10
TZNAME:CET
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20190207T214252Z
UID:F92DD3DC-55F2-4445-AD94-F33A95B5B058
DTSTART;TZID=CET:20180919T150000
DTEND;TZID=CET:20180919T155000
DESCRIPTION:An online fault detection and subsequent error correction becom
 es necessary on a wide scale. But now the extra power needed for fault tol
 erant computing becomes a nightmare\, since extra power and extra heat pro
 motes aging effects strongly.\n\nFirst\, methods of fault detection and er
 ror correction that get along with only a small extra power budget were de
 veloped. Unfortunately\, they are not as powerful\, robust and universally
  applicable as\, for example\, triplication plus majority vote (TMR)\, whi
 ch consumes more than triple power.\n\nThe second approach to the solution
  is the concept of “error resilience”. It is based on the observation 
 that\, depending on function and application of a circuit\, a limited numb
 er of faults may be acceptable for some time without total system failure.
  If the overall systems can become aware of its own fault status\, accepta
 nce of some faults followed by a process of self-repair by re-organization
  during a time slot when the system is “at rest” may be a partial solu
 tion. Then only those parts of a digital system\, where single or multiple
  bit errors will damage the function directly and critically\, will need t
 raditional “fast and hot” methods of error detection and error correct
 ion.\n\nSpeaker(s): Heinrich Theodor Vierhaus\, \n\nRoom: 201\, Bldg: Cent
 re of Mechatronics\, Biomechanics and Nanoengineering\, POZNAN UNIVERSITY 
 OF TECHNOLOGY\, UL. JANA PAWŁA II 24\, Poznan\, Wielkopolskie\, Poland\, 
 60-965
LOCATION:Room: 201\, Bldg: Centre of Mechatronics\, Biomechanics and Nanoen
 gineering\, POZNAN UNIVERSITY OF TECHNOLOGY\, UL. JANA PAWŁA II 24\, Pozn
 an\, Wielkopolskie\, Poland\, 60-965
ORGANIZER:tomasz.marciniak@put.poznan.pl
SEQUENCE:0
SUMMARY:Migrating Electronic Systems from Fault Tolerant Computing to Error
  Resilience 
URL;VALUE=URI:https://events.vtools.ieee.org/m/191258
X-ALT-DESC:Description: <br /><p>An online fault detection and subsequent e
 rror correction becomes necessary on a wide scale. But now the extra power
  needed for fault tolerant computing becomes a nightmare\, since extra pow
 er and extra heat promotes aging effects strongly.</p>\n<p>First\, methods
  of fault detection and error correction that get along with only a small 
 extra power budget were developed. Unfortunately\, they are not as powerfu
 l\, robust and universally applicable as\, for example\, triplication plus
  majority vote (TMR)\, which consumes more than triple power.</p>\n<p>The 
 second approach to the solution is the concept of &ldquo\;error resilience
 &rdquo\;. It is based on the observation that\, depending on function and 
 application of a circuit\, a limited number of faults may be acceptable fo
 r some time without total system failure. If the overall systems can becom
 e aware of its own fault status\, acceptance of some faults followed by a 
 process of self-repair by re-organization during a time slot when the syst
 em is &ldquo\;at rest&rdquo\; may be a partial solution. Then only those p
 arts of a digital system\, where single or multiple bit errors will damage
  the function directly and critically\, will need traditional &ldquo\;fast
  and hot&rdquo\; methods of error detection and error correction.</p>
END:VEVENT
END:VCALENDAR