BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:Asia/Calcutta
BEGIN:STANDARD
DTSTART:19451014T230000
TZOFFSETFROM:+0630
TZOFFSETTO:+0530
TZNAME:IST
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BEGIN:VEVENT
DTSTAMP:20190315T163918Z
UID:DBB7B29A-649A-4997-8335-258B5DD0400B
DTSTART;TZID=Asia/Calcutta:20190222T090000
DTEND;TZID=Asia/Calcutta:20190223T170000
DESCRIPTION:Workshop covers topics in detail about\n\n-&gt; Brushing up Digita
 l Design Basics (Combinational and Sequential)\, RTL Design (Industry Orie
 nted Design Styles and Coding)\, Verification\, Synthesis Flow\, Design fo
 r test Flow.\n\nWorkshop Topics\n\nIntroduction to VLSI Design (ASIC Desig
 n Flow and FPGA Design Flow)\n\nASIC Design Flow (Design For Verification\
 , Design For Synthesis\, Design For Test\, Physical Design).\n\nRTL Design
  Using Verilog HDL\n\nState Machine Coding\n\nWriting Effective Testbenche
 s Using Verilog\n\nGate Level Simulations\n\nBasics Of Static Timing Analy
 sis\n\nIntroduction to System Verilog\n\nAssertion Based Verification (ABV
 )\n\nVerification Methodologies (OVM/UVM)\n\nCode Coverage and Functional 
 Coverage\n\nApplications of VLSI Technology in Artificial Intelligence\, I
 OT etc.\n\nCareer Opportunities in VLSI and Scope of Projects.\n\nDay1: AS
 IC Design Flow \,RTL Design Using Verilog HDL\, State Machine Coding and W
 riting Logic and Effective Testbenches Using Verilog were covered with num
 erous example problems.\n\nDay 2: Gate Level Simulations\, Basics Of Stati
 c Timing Analysis &amp; Career Opportunities in VLSI and Scope of Projects.Mr.
 Abhay Joshi\,Development chair\,Hyderabad Section\, was invited to interac
 t with our students on 23rd Feb\, 2019 between 11:30AM to 12:30PM on IEEE 
 membership drive\, also shared his industry experience on wireless softwar
 e development in relation to its interface with hardware or HW/SW co desig
 n/co-verification etc.\n\nCo-sponsored by: IEEE GCET - SB\n\nSpeaker(s): A
 vinash Yadlapati\, Abhay Joshi\n\nAgenda: \nThe aim of this workshop is to
  provide hands-on experience on the state-of-the-art Cadence EDA tools for
  VLSI Design. The participants will be able to do mini and major projects 
 and shall subsequently open-up career opportunities for them in Core Elect
 ronics. To get familiarity with the different phases of the ASIC Design Fl
 ow\n\nRoom: vlsi lab\, Bldg: I\, Geethanjali college of engineering and te
 chnology\, cheeryal(V)\, Keesara (M)\, Medchal district\, Hyderabad\, Andh
 ra Pradesh\, India\, 501301
LOCATION:Room: vlsi lab\, Bldg: I\, Geethanjali college of engineering and 
 technology\, cheeryal(V)\, Keesara (M)\, Medchal district\, Hyderabad\, An
 dhra Pradesh\, India\, 501301
ORGANIZER:ieeesb.gcet16@gmail.com
SEQUENCE:5
SUMMARY:“Two-day Workshop in VLSI Design with hands-on sessions using Cad
 ence Tools” in collaboration with IEEE CAS Student chapter-GCET
URL;VALUE=URI:https://events.vtools.ieee.org/m/195592
X-ALT-DESC:Description: &lt;br /&gt;&lt;p&gt;Workshop covers topics in detail about&lt;/p&gt;
 \n&lt;p&gt;&amp;nbsp\;-&amp;gt\; Brushing up Digital Design Basics (Combinational and Se
 quential)\, RTL Design (Industry Oriented Design Styles and Coding)\, Veri
 fication\, Synthesis Flow\, &amp;nbsp\;Design for test Flow.&lt;/p&gt;\n&lt;p&gt;&amp;nbsp\;&lt;/
 p&gt;\n&lt;p&gt;&amp;nbsp\;Workshop Topics&lt;/p&gt;\n&lt;p&gt;Introduction to VLSI Design (ASIC De
 sign Flow and FPGA Design Flow)&lt;/p&gt;\n&lt;p&gt;ASIC Design Flow (Design For Verif
 ication\, Design For Synthesis\, Design For Test\, Physical Design).&lt;/p&gt;\n
 &lt;p&gt;RTL Design Using Verilog HDL&lt;/p&gt;\n&lt;p&gt;State Machine Coding&lt;/p&gt;\n&lt;p&gt;Writi
 ng Effective Testbenches Using Verilog&lt;/p&gt;\n&lt;p&gt;Gate Level Simulations&lt;/p&gt;\
 n&lt;p&gt;Basics Of Static Timing Analysis&lt;/p&gt;\n&lt;p&gt;Introduction to System Verilo
 g&lt;/p&gt;\n&lt;p&gt;Assertion Based Verification (ABV)&lt;/p&gt;\n&lt;p&gt;Verification Methodol
 ogies (OVM/UVM)&lt;/p&gt;\n&lt;p&gt;Code Coverage and Functional Coverage&lt;/p&gt;\n&lt;p&gt;Appl
 ications of VLSI Technology in Artificial Intelligence\, IOT etc.&lt;/p&gt;\n&lt;p&gt;
 Career Opportunities in VLSI and Scope of Projects.&lt;/p&gt;\n&lt;p&gt;Day1: ASIC Des
 ign Flow \,RTL Design Using Verilog HDL\, State Machine Coding and Writing
  Logic and Effective Testbenches Using Verilog were covered with numerous 
 example problems.&lt;/p&gt;\n&lt;p&gt;Day 2: Gate Level Simulations\, Basics Of Static
  Timing Analysis &amp;amp\; Career Opportunities in VLSI and Scope of Projects
 .Mr.Abhay Joshi\,Development chair\,Hyderabad Section\, was invited to int
 eract with our students on 23rd Feb\, 2019 between 11:30AM to 12:30PM on I
 EEE membership drive\, also shared his industry experience on wireless sof
 tware development in relation to its interface with hardware or HW/SW co d
 esign/co-verification etc.&lt;/p&gt;\n&lt;p&gt;&amp;nbsp\;&lt;/p&gt;&lt;br /&gt;&lt;br /&gt;Agenda: &lt;br /&gt;&lt;p
 &gt;The aim of this workshop is to provide hands-on experience on the state-o
 f-the-art Cadence EDA tools for VLSI Design. The participants will be able
  to do mini and major projects and shall subsequently open-up career oppor
 tunities for them in Core Electronics. To get familiarity with the differe
 nt phases of the ASIC Design Flow&lt;/p&gt;
END:VEVENT
END:VCALENDAR