BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:Europe/Berlin
BEGIN:DAYLIGHT
DTSTART:20190331T030000
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3
TZNAME:CEST
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BEGIN:STANDARD
DTSTART:20191027T020000
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
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BEGIN:VEVENT
DTSTAMP:20191217T175605Z
UID:3D39CF54-1BAD-4E88-95FF-39D759A445E2
DTSTART;TZID=Europe/Berlin:20190409T150000
DTEND;TZID=Europe/Berlin:20190410T183000
DESCRIPTION:Lectures on Microelectronic Circuits Design.\n\nDuring this mee
 ting Randy Caplan (CEO\, Silicon Creations) will give two talks on Phase L
 ocked Loop (PLL) Design.\n\nSpeaker(s): Randy Caplan (Silicon Creations)\,
  \n\nAgenda: \n15:00 - 16:30 - Randy Caplan (Silicon Creations): Phase Loc
 ked Loop Design (part 1)\n16:30 - 16:45 - Coffee Break\n16:45 - 18:30 - Ra
 ndy Caplan (Silicon Creations): Phase Locked Loop Design (part 2)\n\nRoom:
  auditorium 121\, Bldg: B-1\, AGH University of Science and Technology\, C
 racow\, Malopolskie\, Poland\, 30-059
LOCATION:Room: auditorium 121\, Bldg: B-1\, AGH University of Science and T
 echnology\, Cracow\, Malopolskie\, Poland\, 30-059
ORGANIZER:kasinski@agh.edu.pl
SEQUENCE:1
SUMMARY:Phase Locked Loop Design
URL;VALUE=URI:https://events.vtools.ieee.org/m/195956
X-ALT-DESC:Description: <br /><p>Lectures on Microelectronic Circuits Desig
 n.</p>\n<p>During this meeting Randy Caplan (CEO\, Silicon Creations) will
  give two talks on Phase Locked Loop (PLL) Design.</p><br /><br />Agenda: 
 <br /><p>15:00 - 16:30 - Randy Caplan (Silicon Creations): Phase Locked Lo
 op Design (part 1)<br />16:30 - 16:45 - Coffee Break<br />16:45 - 18:30 - 
 Randy Caplan (Silicon Creations): Phase Locked Loop Design (part 2)</p>
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