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DTSTART:20190331T030000
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DTSTART:20191027T020000
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DTSTAMP:20190626T191717Z
UID:BE4C0317-F775-4068-98E2-A3102B528CDF
DTSTART;TZID=Europe/Zurich:20190626T173000
DTEND;TZID=Europe/Zurich:20190626T183000
DESCRIPTION:Dear Colleagues\,\nCSEM stand with a long Experience in ultra-l
 ow-power digital implementation.\n[Since the 80's\, and the pioneer work o
 f CSEM\,](0.1109/ISSCC.1990.110213) Technology did not stand still.\n\nTod
 ay's FinFet\, FDSOI\, SOTB offers improved opportunities. This work exploi
 t strong body factor of deeply-depleted channel CMOS at 0.5V to compensate
  frequency over PVT to ±6%\, achieving 30x frequency and 20x leakage scal
 ing in a 2.56uW/MHz RISC-Core with 3.13nW/kB 2.5uW/MHz SRAM. The whole sys
 tem offer Frequency-leakage configurability implemented by current-control
 led adaptive body bias at a fixed supply voltage.\n\nThe paper presented a
 s of CICC 2019\, set a World record for MCU Energy efficiency.\n\nWe look 
 forward to hear from Marc.\n\nSpeaker(s): Marc Pons\, \n\nRoom: E81\, Bldg
 : ETZ Building Floor E\, ETH Zurich IIS Departement\, Gloriastrasse\, 35\,
  Zurich\, Switzerland\, Switzerland\, 8092
LOCATION:Room: E81\, Bldg: ETZ Building Floor E\, ETH Zurich IIS Departemen
 t\, Gloriastrasse\, 35\, Zurich\, Switzerland\, Switzerland\, 8092
ORGANIZER:mathieu.coustans@gmail.com
SEQUENCE:3
SUMMARY:IEEE SWISS SSCS TALK : 55nm DDC Subthrehold MCU 2.5uA/MHZ by Marc P
 ons (Senior Engineer CSEM)
URL;VALUE=URI:https://events.vtools.ieee.org/m/199587
X-ALT-DESC:Description: <br /><p>Dear Colleagues\,</p>\n<div>CSEM stand wit
 h a long Experience in ultra-low-power digital implementation.</div>\n<div
 ><a href="0.1109/ISSCC.1990.110213">Since the 80's\, and the pioneer work 
 of CSEM\,</a> Technology did not stand still.</div>\n<div>&nbsp\;</div>\n<
 div>Today's FinFet\, FDSOI\, SOTB offers improved opportunities. This work
 &nbsp\;exploit strong body factor of deeply-depleted channel CMOS at 0.5V 
 to compensate frequency over PVT&nbsp\;to &plusmn\;6%\, achieving 30x freq
 uency and 20x leakage scaling in a 2.56uW/MHz RISC-Core with 3.13nW/kB 2.5
 uW/MHz&nbsp\;SRAM. The whole system offer Frequency-leakage configurabilit
 y implemented by current-controlled adaptive body bias at a fixed supply&n
 bsp\;voltage.</div>\n<div>&nbsp\;</div>\n<div>The paper presented as of CI
 CC 2019\, set a&nbsp\;World record for MCU Energy efficiency.</div>\n<div>
 &nbsp\;</div>\n<div>We look forward to hear from Marc.</div>
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