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DTSTART:20190331T030000
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DTSTART:20191027T020000
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BEGIN:VEVENT
DTSTAMP:20191217T175411Z
UID:3A5A297F-14D8-45E7-B7E6-9A819502AE74
DTSTART;TZID=Europe/Warsaw:20190730T090000
DTEND;TZID=Europe/Warsaw:20190731T123000
DESCRIPTION:2-day seminar on ESD given by dr Charvaka Duvvury. Details can 
 be found in the agenda.\n\nCo-sponsored by: Silicon Creations \n\nSpeaker(
 s): Charvaka Duvvury \, \n\nAgenda: \nDay 1\n9:00 to 9:30: Fundamentals of
  ESD\, EOS\, Latchup . ESD vs. IC Reliability\n9:30 to 10:30: ESD in Manuf
 acturing. ESD Stress Models. ESD Test Standards. ESD Physics and High Curr
 ent Behavior. ESD Characterization with Pulse Testing\n10:30 to 11:00 Coff
 ee Break\n11:00 to 12:30: Process Technology Effects. Basic Protection Des
 igns for HBM/CDM. Methods for ESD Layout and Optimization. Latchup Design 
 and Layout Optimization. Failure Analysis and Lessons Learned\n12:30to 14:
 00 Lunch Break\n14:00 to 15:30: Advanced Protection Design Options. Capaci
 tance Trade-off. Simulations of Protection Clamps. Analog Designs. Chip ES
 D Design Techniques\n15:30 PM to 16:00 Coffee Break\n16:00 to 16:30: RF De
 signs. Mixed Voltage and High Voltage Designs.\n16:30 to 17:30: Advanced T
 echnology Effects . High Speed IO Protection. CDM Package Effects and Desi
 gn Optimization.\n\nDay 2\n9:00 to 9:30 Review of Day 1 Concepts\n9:30 to 
 10:30: FinFET Technology and ESD Design\n10:30 to 11:00: Coffee Break\n11:
 00 to 12:00: SOI ESD Elements. SOI ESD Design Methods.\n12:00 to 12:30: Sy
 stem Level ESD with IC Interface. On-Chip vs\, Off-Chip System Protection.
  USB/HDMI Protection\, and Antenna Protection. EOS Effects. Good Design Pr
 inciples.\n\nRoom: H-24 lecture hall\, Bldg: B-1\, AGH University of Scien
 ce and Technology\, Av. Mickiewicza 30\, Cracow\, Malopolskie\, Poland\, 3
 0-059
LOCATION:Room: H-24 lecture hall\, Bldg: B-1\, AGH University of Science an
 d Technology\, Av. Mickiewicza 30\, Cracow\, Malopolskie\, Poland\, 30-059
ORGANIZER:kasinski@agh.edu.pl
SEQUENCE:1
SUMMARY:Seminar on ESD (basics\, circuits\, techniques)
URL;VALUE=URI:https://events.vtools.ieee.org/m/201253
X-ALT-DESC:Description: &lt;br /&gt;&lt;p&gt;2-day seminar on ESD given by dr&amp;nbsp\;Cha
 rvaka Duvvury. Details can be found in the agenda.&lt;/p&gt;&lt;br /&gt;&lt;br /&gt;Agenda: 
 &lt;br /&gt;&lt;div style=&quot;margin: 0px\; font-size: 12pt\; font-family: Calibri\, A
 rial\, Helvetica\, sans-serif\; background-color: #ffffff\;&quot;&gt;&lt;strong&gt;Day 1
 &lt;/strong&gt;&lt;strong&gt;&amp;nbsp\;&lt;/strong&gt;&lt;/div&gt;\n&lt;div style=&quot;margin: 0px\; font-si
 ze: 12pt\; font-family: Calibri\, Arial\, Helvetica\, sans-serif\; backgro
 und-color: #ffffff\;&quot;&gt;&lt;strong style=&quot;font-size: 12pt\;&quot;&gt;9:00 to 9:30:&amp;nbsp
 \;&lt;/strong&gt;&lt;span style=&quot;font-size: 12pt\;&quot;&gt;Fundamentals of ESD\, EOS\, Lat
 chup . ESD vs. IC Reliability&amp;nbsp\;&lt;/span&gt;&lt;/div&gt;\n&lt;div style=&quot;margin: 0px
 \; font-size: 12pt\; font-family: Calibri\, Arial\, Helvetica\, sans-serif
 \; background-color: #ffffff\;&quot;&gt;&lt;strong style=&quot;font-size: 12pt\;&quot;&gt;9:30 to 
 10:30:&amp;nbsp\;&lt;/strong&gt;&lt;span style=&quot;margin: 0px\;&quot;&gt;ESD in Manufacturing.&amp;nb
 sp\;&lt;/span&gt;&lt;span style=&quot;margin: 0px\;&quot;&gt;ESD Stress Models.&amp;nbsp\;&lt;/span&gt;&lt;sp
 an style=&quot;margin: 0px\;&quot;&gt;ESD Test Standards.&amp;nbsp\;&lt;/span&gt;&lt;span style=&quot;mar
 gin: 0px\;&quot;&gt;ESD Physics and High Current Behavior.&amp;nbsp\;&lt;/span&gt;&lt;span styl
 e=&quot;margin: 0px\;&quot;&gt;ESD Characterization with Pulse Testing&amp;nbsp\;&lt;/span&gt;&lt;/d
 iv&gt;\n&lt;div style=&quot;margin: 0px\; font-size: 12pt\; font-family: Calibri\, Ar
 ial\, Helvetica\, sans-serif\; background-color: #ffffff\;&quot;&gt;&lt;strong style=
 &quot;font-size: 12pt\;&quot;&gt;10:30 to 11:00 Coffee Break&amp;nbsp\;&lt;/strong&gt;&lt;/div&gt;\n&lt;di
 v style=&quot;margin: 0px\; font-size: 12pt\; font-family: Calibri\, Arial\, He
 lvetica\, sans-serif\; background-color: #ffffff\;&quot;&gt;&lt;strong style=&quot;font-si
 ze: 12pt\;&quot;&gt;11:00 to 12:30:&amp;nbsp\;&lt;/strong&gt;&lt;span style=&quot;margin: 0px\;&quot;&gt;Pro
 cess Technology Effects.&amp;nbsp\;&lt;/span&gt;&lt;span style=&quot;margin: 0px\;&quot;&gt;Basic Pr
 otection Designs for HBM/CDM.&amp;nbsp\;&lt;/span&gt;&lt;span style=&quot;margin: 0px\;&quot;&gt;Met
 hods for ESD Layout and Optimization.&amp;nbsp\;&lt;/span&gt;&lt;span style=&quot;margin: 0p
 x\;&quot;&gt;Latchup Design and Layout Optimization.&amp;nbsp\;&lt;/span&gt;&lt;span style=&quot;mar
 gin: 0px\;&quot;&gt;Failure Analysis and Lessons Learned&amp;nbsp\;&amp;nbsp\;&lt;/span&gt;&lt;/div
 &gt;\n&lt;div style=&quot;margin: 0px\; font-size: 12pt\; font-family: Calibri\, Aria
 l\, Helvetica\, sans-serif\; background-color: #ffffff\;&quot;&gt;&lt;strong style=&quot;f
 ont-size: 12pt\;&quot;&gt;12:30to 14:00 Lunch Break&amp;nbsp\;&lt;/strong&gt;&lt;/div&gt;\n&lt;div st
 yle=&quot;margin: 0px\; font-size: 12pt\; font-family: Calibri\, Arial\, Helvet
 ica\, sans-serif\; background-color: #ffffff\;&quot;&gt;&lt;span style=&quot;margin: 0px\;
 &quot;&gt;&lt;strong&gt;14:00 to 15:30:&amp;nbsp\;&lt;/strong&gt;&lt;/span&gt;&lt;span style=&quot;margin: 0px\;
 &quot;&gt;Advanced Protection Design Options.&amp;nbsp\;&lt;/span&gt;&lt;span style=&quot;margin: 0p
 x\;&quot;&gt;Capacitance Trade-off.&amp;nbsp\;&lt;/span&gt;&lt;span style=&quot;margin: 0px\;&quot;&gt;Simul
 ations of Protection Clamps.&amp;nbsp\;&lt;/span&gt;&lt;span style=&quot;margin: 0px\;&quot;&gt;Anal
 og Designs.&amp;nbsp\;&lt;/span&gt;&lt;span style=&quot;margin: 0px\;&quot;&gt;Chip ESD Design Techn
 iques&amp;nbsp\;&lt;/span&gt;&lt;/div&gt;\n&lt;div style=&quot;margin: 0px\; font-size: 12pt\; fon
 t-family: Calibri\, Arial\, Helvetica\, sans-serif\; background-color: #ff
 ffff\;&quot;&gt;&lt;strong style=&quot;font-size: 12pt\;&quot;&gt;15:30 PM to 16:00&amp;nbsp\;&lt;span st
 yle=&quot;margin: 0px\; background-color: #ffffff\;&quot;&gt;Coffee Break&amp;nbsp\;&lt;/span&gt;
 &lt;/strong&gt;&lt;/div&gt;\n&lt;div style=&quot;margin: 0px\; font-size: 12pt\; font-family: 
 Calibri\, Arial\, Helvetica\, sans-serif\; color: #000000\;&quot;&gt;&lt;span style=&quot;
 margin: 0px\;&quot;&gt;&lt;strong&gt;16:00 to 16:30:&amp;nbsp\;&lt;/strong&gt;&lt;/span&gt;&lt;span style=&quot;
 margin: 0px\;&quot;&gt;RF Designs.&amp;nbsp\;&lt;/span&gt;&lt;span style=&quot;margin: 0px\;&quot;&gt;Mixed 
 Voltage and High Voltage Designs.&lt;/span&gt;&lt;/div&gt;\n&lt;div style=&quot;margin: 0px\; 
 font-size: 12pt\; font-family: Calibri\, Arial\, Helvetica\, sans-serif\; 
 color: #000000\;&quot;&gt;&lt;strong style=&quot;font-size: 12pt\;&quot;&gt;16:30 to 17:30:&amp;nbsp\;
 &lt;/strong&gt;&lt;span style=&quot;margin: 0px\;&quot;&gt;Advanced Technology Effects .&amp;nbsp\;&lt;
 /span&gt;&lt;span style=&quot;margin: 0px\;&quot;&gt;High Speed IO Protection.&amp;nbsp\;&lt;/span&gt;&lt;
 span style=&quot;margin: 0px\;&quot;&gt;CDM Package Effects and Design Optimization.&amp;nb
 sp\;&lt;/span&gt;&lt;/div&gt;\n&lt;div style=&quot;margin: 0px\; font-size: 12pt\; font-family
 : Calibri\, Arial\, Helvetica\, sans-serif\; background-color: #ffffff\;&quot;&gt;
 &amp;nbsp\;&lt;/div&gt;\n&lt;div style=&quot;margin: 0px\; font-size: 12pt\; font-family: Ca
 libri\, Arial\, Helvetica\, sans-serif\; background-color: #ffffff\;&quot;&gt;&lt;spa
 n style=&quot;margin: 0px\;&quot;&gt;&lt;strong&gt;Day 2&amp;nbsp\;&lt;/strong&gt;&lt;/span&gt;&lt;/div&gt;\n&lt;div s
 tyle=&quot;margin: 0px\; font-size: 12pt\; font-family: Calibri\, Arial\, Helve
 tica\, sans-serif\; background-color: #ffffff\;&quot;&gt;&lt;span style=&quot;margin: 0px\
 ;&quot;&gt;&lt;strong&gt;9:00 to 9:30&amp;nbsp\;&lt;/strong&gt;&lt;/span&gt;&lt;span style=&quot;font-size: 12pt
 \;&quot;&gt;Review of Day 1 Concepts&amp;nbsp\;&lt;/span&gt;&lt;/div&gt;\n&lt;div style=&quot;margin: 0px\
 ; font-size: 12pt\; font-family: Calibri\, Arial\, Helvetica\, sans-serif\
 ; background-color: #ffffff\;&quot;&gt;&lt;strong style=&quot;font-size: 12pt\;&quot;&gt;9:30 to 1
 0:30:&amp;nbsp\;&lt;/strong&gt;&lt;span style=&quot;margin: 0px\;&quot;&gt;FinFET Technology and ESD
  Design&lt;br /&gt;&lt;/span&gt;&lt;strong style=&quot;font-size: 12pt\;&quot;&gt;10:30 to 11:00:&amp;nbsp
 \;&lt;strong&gt;&lt;span style=&quot;margin: 0px\; background-color: #ffffff\;&quot;&gt;Coffee B
 reak&lt;/span&gt;&lt;/strong&gt;&lt;/strong&gt;&lt;/div&gt;\n&lt;div style=&quot;margin: 0px\; font-size: 
 12pt\; font-family: Calibri\, Arial\, Helvetica\, sans-serif\; color: #000
 000\;&quot;&gt;&lt;span style=&quot;margin: 0px\;&quot;&gt;&lt;strong&gt;11:00 to 12:00:&amp;nbsp\;&lt;/strong&gt;
 &lt;/span&gt;SOI ESD Elements.&amp;nbsp\;SOI ESD Design Methods.&lt;/div&gt;\n&lt;div style=&quot;
 margin: 0px\; font-size: 12pt\; font-family: Calibri\, Arial\, Helvetica\,
  sans-serif\; color: #000000\;&quot;&gt;&lt;strong style=&quot;font-size: 12pt\;&quot;&gt;12:00 to
  12:30:&amp;nbsp\;&lt;/strong&gt;System Level ESD with IC Interface.&amp;nbsp\;On-Chip v
 s\, Off-Chip System Protection.&amp;nbsp\;USB/HDMI Protection\, and Antenna Pr
 otection. EOS Effects. Good Design Principles.&lt;/div&gt;
END:VEVENT
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