BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT DTSTART:20190310T030000 TZOFFSETFROM:-0800 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:PDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20191103T010000 TZOFFSETFROM:-0700 TZOFFSETTO:-0800 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:PST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20190927T152251Z UID:7B41B0EB-42E6-4AFE-89A2-6167C68650D8 DTSTART;TZID=America/Los_Angeles:20190823T100000 DTEND;TZID=America/Los_Angeles:20190824T120000 DESCRIPTION:Jitter refers to deviation from ideal timing in clock and data transitions. In wireline communications\, jitter reduces the timing margin available for clock and data recovery (CDR) circuits and poses significan t challenges to signal integrity as the data rates march towards 100Gb/s/l ane and beyond. In this talk\, we first review the basic definitions of ji tter and its properties\, the relationship between jitter and phase noise\ , and the effects of jitter on CDR and other building blocks of a wireline system. We then describe the concept of jitter transfer\, jitter generati on\, and jitter tolerance curves\, and the methods of characterizing\, mod eling\, and simulating jitter. Finally\, we present some recent works on j itter measurement and jitter mitigation techniques that are used to optimi ze the link performance.\n\nQualcomm AZ-Auditorium (10155 Pacific Heights Blvd\, San Diego\, CA 92121)\, San diego\, California\, United States LOCATION:Qualcomm AZ-Auditorium (10155 Pacific Heights Blvd\, San Diego\, C A 92121)\, San diego\, California\, United States ORGANIZER:alvin.loke@alumni.stanford.edu SEQUENCE:1 SUMMARY:Basics of Jitter in Wireline Communications URL;VALUE=URI:https://events.vtools.ieee.org/m/202740 X-ALT-DESC:Description: <br /><p>Jitter refers to deviation from ideal timi ng in clock and data transitions. In wireline communications\, jitter redu ces the timing margin available for clock and data recovery (CDR) circuits and poses significant challenges to signal integrity as the data rates ma rch towards 100Gb/s/lane and beyond. In this talk\, we first review the ba sic definitions of jitter and its properties\, the relationship between ji tter and phase noise\, and the effects of jitter on CDR and other building blocks of a wireline system. We then describe the concept of jitter trans fer\, jitter generation\, and jitter tolerance curves\, and the methods of characterizing\, modeling\, and simulating jitter. Finally\, we present s ome recent works on jitter measurement and jitter mitigation techniques th at are used to optimize the link performance.</p> END:VEVENT END:VCALENDAR