BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:US/Pacific BEGIN:DAYLIGHT DTSTART:20200308T030000 TZOFFSETFROM:-0800 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:PDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20191103T010000 TZOFFSETFROM:-0700 TZOFFSETTO:-0800 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:PST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20191107T174717Z UID:EB009564-F3C1-44B7-BF45-11DFAFB346DE DTSTART;TZID=US/Pacific:20191106T183000 DTEND;TZID=US/Pacific:20191106T213000 DESCRIPTION:The PDN delivers power to the on-die CMOS circuits. CMOS circui ts are sensitive to the power supply voltage because of Fmax\, Vmin and Ji tter considerations. Logic core speed is limited by the instantaneous powe r supply voltage including PDN voltage droops. The power supply voltage is often raised up to overcome PDN voltage droops to enable the on-die circu it voltage to stay above the minimum voltage (Vmin) where the circuits wil l run at rated clock speed (a high percentage of Fmax). These are the impo rtant PDN considerations for all CMOS circuits.\n\nDC current is easy to d eliver from the voltage regulator to the CMOS load and only suffers IR (cu rrent times resistance) loss. The major PDN problem is that current and po wer transients\, associated with rapidly changing load conditions\, demand a time varying amount current from the reactive (inductance and capacitan ce) nature of the PDN. Power integrity is all about managing the R\, L and C properties of the PDN such that the transient currents can be delivered to the load with acceptable voltage droop. For IO circuits\, the PDN prop erties are used to manage PDN induced jitter. All power supply design begi ns with the calculation of a target impedance\, which is a strong indicato r of the required PDN performance over a broad frequency range. It is used to manage PDN cost\, performance and risk.\n\nThe PDN is designed and man aged in the frequency domain where the goal is to manage R\, L and C in a way that is close to the target impedance. A particular challenge is “Ba ndini Mountain” where the on-die capacitance and the bump loop inductanc e form an impedance peak that limits product performance and is expensive to fix. At the end of the day\, all CMOS circuits function in the time dom ain. In the time domain\, it is important to pay attention to the voltage responses from impulse\, step and resonance current waveforms. They are in timately related to the frequency domain impedance profile and determine P DN costs\, product power consumption and performance levels of the product .\n\n \n\nCo-sponsored by: Yi Cao\n\nSpeaker(s): Larry D Smith\, \n\nAge nda: \n6:00pm light snacks and networking\n\n6:30pm Meeting/Presentation b egins\n\n8:30pm Adjourn\n\nFree and dinner will be provided.\n\nAdvanced T est Equipment Corp\, San Diego\, California\, United States\, 92121 LOCATION:Advanced Test Equipment Corp\, San Diego\, California\, United Sta tes\, 92121 ORGANIZER:yi.cao.us@ieee.org SEQUENCE:4 SUMMARY:Principles of Power Integrity for PDN Design URL;VALUE=URI:https://events.vtools.ieee.org/m/208838 X-ALT-DESC:Description: <br /><p>The PDN delivers power to the on-die CMOS circuits. CMOS circuits are sensitive to the power supply voltage because of Fmax\, Vmin and Jitter considerations. Logic core speed is limited by t he instantaneous power supply voltage including PDN voltage droops. The po wer supply voltage is often raised up to overcome PDN voltage droops to en able the on-die circuit voltage to stay above the minimum voltage (Vmin) w here the circuits will run at rated clock speed (a high percentage of Fmax ). These are the important PDN considerations for all CMOS circuits.</p>\n <p>&nbsp\;</p>\n<p>DC current is easy to deliver from the voltage regulato r to the CMOS load and only suffers IR (current times resistance) loss. Th e major PDN problem is that current and power transients\, associated with rapidly changing load conditions\, demand a time varying amount current f rom the reactive (inductance and capacitance) nature of the PDN. Power int egrity is all about managing the R\, L and C properties of the PDN such th at the transient currents can be delivered to the load with acceptable vol tage droop. For IO circuits\, the PDN properties are used to manage PDN in duced jitter. All power supply design begins with the calculation of a tar get impedance\, which is a strong indicator of the required PDN performanc e over a broad frequency range. It is used to manage PDN cost\, performanc e and risk.</p>\n<p>&nbsp\;</p>\n<p>The PDN is designed and managed in the frequency domain where the goal is to manage R\, L and C in a way that is close to the target impedance. A particular challenge is &ldquo\;Bandini Mountain&rdquo\; where the on-die capacitance and the bump loop inductance form an impedance peak that limits product performance and is expensive t o fix. At the end of the day\, all CMOS circuits function in the time doma in. In the time domain\, it is important to pay attention to the voltage r esponses from impulse\, step and resonance current waveforms. They are int imately related to the frequency domain impedance profile and determine PD N costs\, product power consumption and performance levels of the product. </p>\n<p> &nbsp\;</p><br /><br />Agenda: <br /><div class="heading">&nbs p\;</div>\n<p>6:00pm&nbsp\; light snacks and networking</p>\n<p>6:30pm&nbs p\; Meeting/Presentation begins</p>\n<p>8:30pm&nbsp\; Adjourn</p>\n<p>Free and dinner will be provided.</p> END:VEVENT END:VCALENDAR