BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Europe/Warsaw BEGIN:DAYLIGHT DTSTART:20200329T030000 TZOFFSETFROM:+0100 TZOFFSETTO:+0200 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3 TZNAME:CEST END:DAYLIGHT BEGIN:STANDARD DTSTART:20191027T020000 TZOFFSETFROM:+0200 TZOFFSETTO:+0100 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10 TZNAME:CET END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20191217T170914Z UID:D3FF99FF-DE6D-447F-BC89-4A510AA821D8 DTSTART;TZID=Europe/Warsaw:20191203T170000 DTEND;TZID=Europe/Warsaw:20191203T190000 DESCRIPTION:Internet-of-Things (IoT) imposes severe requirements on ultra-l ow power consumption of radio frequency (RF) transceivers. Battery life is critical in these applications and can be extended by lowering supply vol tage to reduce power consumption. In the receiver part of the radio\, the analog front-end section is the most power-hungry subsystem and has receiv ed a lot of attention lately\, mainly from the analog continuous-time poin t of view. Advances in discrete-time receiver designs\, however\, offer ne w alternatives with simpler and technology-scalable switched-capacitor cir cuits and easy calibration of intermediate frequency and band-pass selecti on based on capacitor ratios\, which are less sensitive to process variati ons. New passive charge-domain switched-capacitor (SC) filter topologies a nd accurate control of sampling rates\, both of which benefit from technol ogy scaling and enable easier-to-design low-power solutions\, have been in troduced. Another important aspect is a new capability of achieving analog -to-digital conversion (ADC) using passive SC sigma-delta oversampling tec hniques. A new architecture was recently proposed and realized in 28nm CMO S. It contains only switches\, capacitors and one comparator\, thus being greatly amenable to nanoscale CMOS process nodes.\n\nSpeaker(s): prof. Bog dan Staszewski (University College Dublin\, \n\nRoom: H24 (1st floor)\, Bl dg: B1\, AGH University of Science and Technology\, Av. Mickiewicza 30\, K rakow\, Malopolskie\, Poland\, 30-059 LOCATION:Room: H24 (1st floor)\, Bldg: B1\, AGH University of Science and T echnology\, Av. Mickiewicza 30\, Krakow\, Malopolskie\, Poland\, 30-059 ORGANIZER:kasinski@agh.edu.pl SEQUENCE:2 SUMMARY:Lecture on Discrete-Time Receivers and ADC for the Internet-of-Thin gs URL;VALUE=URI:https://events.vtools.ieee.org/m/212217 X-ALT-DESC:Description: <br /><p>Internet-of-Things (IoT) imposes severe re quirements on ultra-low power consumption of radio frequency (RF) transcei vers. Battery life is critical in these applications and can be extended b y lowering supply voltage to reduce power consumption. In the receiver par t of the radio\, the analog front-end section is the most power-hungry sub system and has received a lot of attention lately\, mainly from the analog continuous-time point of view. Advances in discrete-time receiver designs \, however\, offer new alternatives with simpler and technology-scalable s witched-capacitor circuits and easy calibration of intermediate frequency and band-pass selection based on capacitor ratios\, which are less sensiti ve to process variations. New passive charge-domain switched-capacitor (SC ) filter topologies and accurate control of sampling rates\, both of which benefit from technology scaling and enable easier-to-design low-power sol utions\, have been introduced. Another important aspect is a new capabilit y of achieving analog-to-digital conversion (ADC) using passive SC sigma-d elta oversampling techniques. A new architecture was recently proposed and realized in 28nm CMOS. It contains only switches\, capacitors and one com parator\, thus being greatly amenable to nanoscale CMOS process nodes.</p> END:VEVENT END:VCALENDAR