BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:US/Pacific BEGIN:DAYLIGHT DTSTART:20200308T030000 TZOFFSETFROM:-0800 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:PDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20191103T010000 TZOFFSETFROM:-0700 TZOFFSETTO:-0800 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:PST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20200221T074415Z UID:ED82D68F-6109-4C4D-8A21-19AD04D1C43E DTSTART;TZID=US/Pacific:20200220T173000 DTEND;TZID=US/Pacific:20200220T200000 DESCRIPTION:Advanced Frequency Synthesis For Digitally Intensive Transmitte rs For IoT And Mm-Wave Radios\, CASS-SCV Multi-Speaker Event\n\nDr. Robert Bogdan Staszewski\, School of Electrical & Electronic Engineering\, Unive rsity College Dublin and\n\nDr. Yizhe Hu\, School of Electrical & Electron ic Engineering\, University College Dublin\n\nEvent Organized By:\n\n[Circ uits and Systems Society](https://site.ieee.org/scv-cas/)(CASS-SCV) of the [IEEE Santa Clara Valley Section](http://sites.ieee.org/scv/)\n\nCo-spons ors:\n\n- [Solid-State Circuits Society(SSCS)](http://sites.ieee.org/scv-s scs/upcoming-events/)\n\n- [Microwave Theory and Techniques (MTT](https:// webinabox.vtools.ieee.org/wibp_home/index/CH06085))\n- [Communication Soci ety (ComSoc)](http://www.comsocscv.org/)\n-\n[Signal Processing Society(SP S)](https://ewh.ieee.org/r6/scv/sps/)\n\nPROGRAM:\n\n5:30 - 6:00 PM Networ king & Refreshments\n\n6:00 - 6:50 PM Lecture 1: "Deep-Subthreshold Operat ion of ADPLLs\, Transmitters and ADCs\," by Dr. Robert Bogdan Staszewski\n \n6:50 - 7:00 PM Q&A\n\n7:00 - 7:50 PM Lecture 2: "A New Type of Frequency Synthesis for RF and mm-Wave: Charge-Sharing Locking\," by Dr. Yizhe Hu\n \n7:50 - 8:00 PM Q&A/Adjourn\n\nLecture 1 (6:00 - 6:50 PM): "Deep-Subthres hold Operation of ADPLLs\, Transmitters and ADCs\," by Dr. Robert Bogdan S taszewski\n\nAbstract:\n\nInternet-of-Things (IoT) devices are meant to be powered by energy harvesters\, which unfortunately tend to generate very little power at very low voltages\, often well below the threshold voltage of CMOS transistors. Hence the need for an ultra-low power (ULP) and ultr a-low voltage (ULV) operation of IoT electronic circuits. This talk presen ts recent breakthroughs in collaboration with TSMC in sub-threshold design s of an all-digital PLL (ADPLL)\, RF Bluetooth transmitter\, and open-loop VCO-based ADC. The supply voltage in these circuits can go to as low as 0 .2V.\n\nBio:\n\n- Bogdan Staszewskireceived B.Sc. (summa cum laude)\, M.Sc . and PhD from University of Texas at Dallas\, USA\, in 1991\, 1992 and 20 02\, respectively. From 1991 to 1995 he was with Alcatel in Richardson\, T exas. He joined Texas Instruments in Dallas\, Texas in 1995. In 1999 he co -started a Digital RF Processor (DRP) group in TI with a mission to invent new digitally intensive approaches to traditional RF functions. Dr. Stasz ewski served as a CTO of the DRP group between 2007 and 2009. In July 2009 he joined Delft University of Technology in the Netherlands where he is c urrently a part-time Full Professor. Since Sept. 2014 he has been a Full P rofessor at University College Dublin (UCD) in Ireland. He has co-authored five books\, seven book chapters\, 300 journal and conference publication s\, and holds 180 issued US patents. His research interests include nanosc ale CMOS architectures and circuits for frequency synthesizers\, transmitt ers and receivers\, as well as quantum computers. He is a co-founder of a startup company Equal1 Labs aiming at building the first practical CMOS qu antum computer.\n\nHe is an IEEE Fellow and a recipient of IEEE Circuits a nd Systems Industrial Pioneer Award (http://ieee-cas.org/industrial-pionee r-award-recipients). He was a TPC Chair of IEEE European Solid-State Circu its Conference (ESSCIRC) in 2019 in Krakow\, Poland.\n\nLecture 2 (7:00 - 7:50 PM): "A New Type of Frequency Synthesis for RF and mm-Wave: Charge-Sh aring Locking\," by Dr. Yizhe Hu\n\nAbstract:\n\nUltra-low jitter (sub-100 fs) frequency synthesis is highly desirable for 5G RF and mm-Wave (mmW) co mmunications to support the complex modulation schemes (e.g. 1024QAM). Our group has recently invented a new charge-sharing locking (CSL) technique to meet these tough requirements. A quadrature CSL prototype was implement ed in TSMC 28nm CMOS and achieves 75fs jitter in 21.7-to-26.5GHz while con suming only 16.5mW. This talk presents the details and gives further insig hts into designing oscillators with ultra-low phase noise in the flicker a nd thermal regions.\n\nBio:\n\nYizhe Hu received the B.Sc. degree (summa c um laude) in microelectronics from Harbin Institute of Technology (HIT)\, Harbin\, China\, in 2013\, and the PhD degree in microelectronics from Uni versity College Dublin (UCD)\, Dublin\, Ireland\, in 2019. He is currently working as a postdoctoral researcher with Prof. R. Bogdan Staszewski in U CD. From 2013 to 2014\, he was with Fudan University\, Shanghai\, China\, where he was involved in RFIC design as a postgraduate researcher. From Ma y 2016 to Oct 2017\, he was consulting for the PLL Group of HiSilicon\, Hu awei Technologies\, China\, designing 16 nm DCOs and ADPLLs. Since June 20 18\, he has been consulting for the Mixed-Signal Design Department\, TSMC\ , for a new type of PLL design. His research interests include RF/mm-wave integrated circuits and systems for wireless communications. Dr. Hu has se rved as a frequent reviewer for the IEEE JSSC\, TCAS-I/II\, and TMTT.\n\nZ oom Broadcast:\n\nLecture will be broadcast live on Zoom and recorded. Ple ase register to receive Zoom conference details one day before the event.\ n\nVenue:\n\n[QualComm Santa Clara\, Building B\, 3165 Kifer Road\, Santa Clara\, CA 95051](https://goo.gl/maps/HDvZvuY4Wym)\n\nAdmission Fee:\n\nAl l admissions free. Suggested donations to cover food and water:\n\nNon-IEE E: $5\, Students (non-IEEE): $3\, IEEE Members (not members of CASS or SSC S): $3\n\nOnline registration is recommended to guarantee seating.\n\nCo-s ponsored by: Solid State Circuits Society (SSCS)\, Microwave Theory and Te chniques Society (MTT)\, Communication Society (ComSoC)\, Signal Processin g Society (SPS)\n\nSpeaker(s): Robert Bogdan Staszewski\, Dr. Yizhe Hu\n\n Agenda: \nAdvanced Frequency Synthesis For Digitally Intensive Transmitter s For IoT And Mm-Wave Radios\, CASS-SCV Multi-Speaker Event\n\nDr. Robert Bogdan Staszewski\, School of Electrical & Electronic Engineering\, Univer sity College Dublin and\n\nDr. Yizhe Hu\, School of Electrical & Electroni c Engineering\, University College Dublin\n\nEvent Organized By:\n\n[Circu its and Systems Society](https://site.ieee.org/scv-cas/)(CASS-SCV) of the [IEEE Santa Clara Valley Section](http://sites.ieee.org/scv/)\n\nCo-sponso rs:\n\n- [Solid-State Circuits Society(SSCS)](http://sites.ieee.org/scv-ss cs/upcoming-events/)\n\n- [Microwave Theory and Techniques (MTT](https://w ebinabox.vtools.ieee.org/wibp_home/index/CH06085))\n- [Communication Socie ty (ComSoc)](http://www.comsocscv.org/)\n-\n[Signal Processing Society(SPS )](https://ewh.ieee.org/r6/scv/sps/)\n\nPROGRAM:\n\n5:30 - 6:00 PM Network ing & Refreshments\n\n6:00 - 6:50 PM Lecture 1: "Deep-Subthreshold Operati on of ADPLLs\, Transmitters and ADCs\," by Dr. Robert Bogdan Staszewski\n\ n6:50 - 7:00 PM Q&A\n\n7:00 - 7:50 PM Lecture 2: "A New Type of Frequency Synthesis for RF and mm-Wave: Charge-Sharing Locking\," by Dr. Yizhe Hu\n\ n7:50 - 8:00 PM Q&A/Adjourn\n\nLecture 1 (6:00 - 6:50 PM): "Deep-Subthresh old Operation of ADPLLs\, Transmitters and ADCs\," by Dr. Robert Bogdan St aszewski\n\nAbstract:\n\nInternet-of-Things (IoT) devices are meant to be powered by energy harvesters\, which unfortunately tend to generate very l ittle power at very low voltages\, often well below the threshold voltage of CMOS transistors. Hence the need for an ultra-low power (ULP) and ultra -low voltage (ULV) operation of IoT electronic circuits. This talk present s recent breakthroughs in collaboration with TSMC in sub-threshold designs of an all-digital PLL (ADPLL)\, RF Bluetooth transmitter\, and open-loop VCO-based ADC. The supply voltage in these circuits can go to as low as 0. 2V.\n\nBio:\n\n- Bogdan Staszewskireceived B.Sc. (summa cum laude)\, M.Sc. and PhD from University of Texas at Dallas\, USA\, in 1991\, 1992 and 200 2\, respectively. From 1991 to 1995 he was with Alcatel in Richardson\, Te xas. He joined Texas Instruments in Dallas\, Texas in 1995. In 1999 he co- started a Digital RF Processor (DRP) group in TI with a mission to invent new digitally intensive approaches to traditional RF functions. Dr. Stasze wski served as a CTO of the DRP group between 2007 and 2009. In July 2009 he joined Delft University of Technology in the Netherlands where he is cu rrently a part-time Full Professor. Since Sept. 2014 he has been a Full Pr ofessor at University College Dublin (UCD) in Ireland. He has co-authored five books\, seven book chapters\, 300 journal and conference publications \, and holds 180 issued US patents. His research interests include nanosca le CMOS architectures and circuits for frequency synthesizers\, transmitte rs and receivers\, as well as quantum computers. He is a co-founder of a s tartup company Equal1 Labs aiming at building the first practical CMOS qua ntum computer.\n\nHe is an IEEE Fellow and a recipient of IEEE Circuits an d Systems Industrial Pioneer Award (http://ieee-cas.org/industrial-pioneer -award-recipients). He was a TPC Chair of IEEE European Solid-State Circui ts Conference (ESSCIRC) in 2019 in Krakow\, Poland.\n\nLecture 2 (7:00 - 7 :50 PM): "A New Type of Frequency Synthesis for RF and mm-Wave: Charge-Sha ring Locking\," by Dr. Yizhe Hu\n\nAbstract:\n\nUltra-low jitter (sub-100f s) frequency synthesis is highly desirable for 5G RF and mm-Wave (mmW) com munications to support the complex modulation schemes (e.g. 1024QAM). Our group has recently invented a new charge-sharing locking (CSL) technique t o meet these tough requirements. A quadrature CSL prototype was implemente d in TSMC 28nm CMOS and achieves 75fs jitter in 21.7-to-26.5GHz while cons uming only 16.5mW. This talk presents the details and gives further insigh ts into designing oscillators with ultra-low phase noise in the flicker an d thermal regions.\n\nBio:\n\nYizhe Hu received the B.Sc. degree (summa cu m laude) in microelectronics from Harbin Institute of Technology (HIT)\, H arbin\, China\, in 2013\, and the PhD degree in microelectronics from Univ ersity College Dublin (UCD)\, Dublin\, Ireland\, in 2019. He is currently working as a postdoctoral researcher with Prof. R. Bogdan Staszewski in UC D. From 2013 to 2014\, he was with Fudan University\, Shanghai\, China\, w here he was involved in RFIC design as a postgraduate researcher. From May 2016 to Oct 2017\, he was consulting for the PLL Group of HiSilicon\, Hua wei Technologies\, China\, designing 16 nm DCOs and ADPLLs. Since June 201 8\, he has been consulting for the Mixed-Signal Design Department\, TSMC\, for a new type of PLL design. His research interests include RF/mm-wave i ntegrated circuits and systems for wireless communications. Dr. Hu has ser ved as a frequent reviewer for the IEEE JSSC\, TCAS-I/II\, and TMTT.\n\nZo om Broadcast:\n\nLecture will be broadcast live on Zoom and recorded. Plea se register to receive Zoom conference details one day before the event.\n \nVenue:\n\n[QualComm Santa Clara\, Building B\, 3165 Kifer Road\, Santa C lara\, CA 95051](https://goo.gl/maps/HDvZvuY4Wym)\n\nAdmission Fee:\n\nAll admissions free. Suggested donations to cover food and water:\n\nNon-IEEE : $5\, Students (non-IEEE): $3\, IEEE Members (not members of CASS or SSCS ): $3\n\nOnline registration is recommended to guarantee seating.\n\nBldg: Building B\, QualComm Santa Clara\, 3165 Kifer Road\, Santa Clara\, Calif ornia\, United States\, 95051 LOCATION:Bldg: Building B\, QualComm Santa Clara\, 3165 Kifer Road\, Santa Clara\, California\, United States\, 95051 ORGANIZER:imran.bashir@ieee.org SEQUENCE:1 SUMMARY:Advanced Frequency Synthesis For Digitally Intensive Transmitters F or IoT And Mm-Wave Radios\, CASS-SCV Multi-Speaker Event URL;VALUE=URI:https://events.vtools.ieee.org/m/218864 X-ALT-DESC:Description: <br /><h2 style="font-weight: 600\;">Advanced Frequ ency Synthesis For Digitally Intensive Transmitters For IoT And Mm-Wave Ra dios\, CASS-SCV Multi-Speaker Event</h2>\n<h3 style="font-weight: 400\;">< strong>Dr. Robert Bogdan Staszewski\,&nbsp\;School of Electrical &amp\; El ectronic Engineering\,&nbsp\;</strong><strong>University College Dublin an d</strong></h3>\n<h3 style="font-weight: 400\;"><strong>Dr.&nbsp\;Yizhe Hu \, School of Electrical &amp\; Electronic Engineering\,&nbsp\;</strong><st rong>University College Dublin</strong></h3>\n<h3 style="font-weight: 400\ ;">Event Organized By:</h3>\n<p style="font-weight: 400\;"><a href="https: //site.ieee.org/scv-cas/">Circuits and Systems Society&nbsp\;</a>(CASS-SCV )&nbsp\;of the&nbsp\;<a href="http://sites.ieee.org/scv/">IEEE Santa Clara Valley Section</a></p>\n<h3 style="font-weight: 400\;">Co-sponsors:</h3>\ n<ul style="font-weight: 400\;">\n<li><a href="http://sites.ieee.org/scv-s scs/upcoming-events/">Solid-State Circuits Society(SSCS)</a></li>\n</ul>\n <ul style="font-weight: 400\;">\n<li><a href="https://webinabox.vtools.iee e.org/wibp_home/index/CH06085">Microwave Theory and Techniques (MTT</a>)</ li>\n<li><a href="http://www.comsocscv.org/">Communication Society (ComSoc )</a></li>\n<li>\n<h3 style="font-weight: 400\;"><a href="https://ewh.ieee .org/r6/scv/sps/">Signal Processing Society(SPS)</a></h3>\n</li>\n</ul>\n< p style="font-weight: 400\;"><strong>PROGRAM:</strong></p>\n<p>5:30 - 6:00 PM Networking &amp\; Refreshments</p>\n<p>6:00 - 6:50 PM Lecture 1: "Deep -Subthreshold Operation of ADPLLs\, Transmitters and ADCs\," by Dr. Robert Bogdan Staszewski</p>\n<p>6:50 - 7:00 PM Q&amp\;A</p>\n<p>7:00 - 7:50 PM Lecture 2: "A&nbsp\;New Type of Frequency Synthesis for RF and mm-Wave: Ch arge-Sharing Locking\," by&nbsp\;Dr. Yizhe Hu</p>\n<p>7:50 - 8:00 PM Q&amp \;A/Adjourn</p>\n<p style="font-weight: 400\;"><strong>Lecture 1 (6:00 - 6 :50 PM): "Deep-Subthreshold Operation of ADPLLs\, Transmitters and ADCs\," by Dr. Robert Bogdan Staszewski</strong></p>\n<p style="font-weight: 400\ ;"><strong>Abstract:</strong></p>\n<p style="font-weight: 400\;">Internet- of-Things (IoT) devices are meant to be powered by energy harvesters\, whi ch unfortunately tend to generate very little power at very low voltages\, often well below the threshold voltage of CMOS transistors. Hence the nee d for an ultra-low power (ULP) and ultra-low voltage (ULV) operation of Io T electronic circuits. This talk presents recent breakthroughs in collabor ation with TSMC in sub-threshold designs of an all-digital PLL (ADPLL)\, R F Bluetooth transmitter\, and open-loop VCO-based ADC. The supply voltage in these circuits can go to as low as 0.2V.</p>\n<h2 style="font-weight: 6 00\;">Bio:</h2>\n<ol start="1995">\n<li style="font-weight: 400\;">Bogdan Staszewskireceived B.Sc. (<em>summa cum laude</em>)\, M.Sc. and PhD from U niversity of Texas at Dallas\, USA\, in 1991\, 1992 and 2002\, respectivel y. From 1991 to 1995 he was with Alcatel in Richardson\, Texas. He joined Texas Instruments in Dallas\, Texas in 1995. In 1999 he co-started a Digit al RF Processor (DRP) group in TI with a mission to invent new digitally i ntensive approaches to traditional RF functions. Dr. Staszewski served as a CTO of the DRP group between 2007 and 2009. In July 2009 he joined Delft University of Technology in the Netherlands where he is currently a part- time Full Professor. Since Sept. 2014 he has been a Full Professor at Univ ersity College Dublin (UCD) in Ireland. He has co-authored five books\, se ven book chapters\, 300 journal and conference publications\, and holds 18 0 issued US patents. His research interests include nanoscale CMOS archite ctures and circuits for frequency synthesizers\, transmitters and receiver s\, as well as quantum computers. He is a co-founder of a startup company Equal1 Labs aiming at building the first practical CMOS quantum computer.< /li>\n</ol>\n<p style="font-weight: 400\;">He is an IEEE Fellow and a reci pient of&nbsp\;IEEE Circuits and Systems Industrial Pioneer Award (http:// ieee-cas.org/industrial-pioneer-award-recipients). He was a TPC Chair of I EEE European Solid-State Circuits Conference (ESSCIRC) in 2019 in Krakow\, Poland.</p>\n<p style="font-weight: 400\;"><strong>Lecture 2 (7:00 - 7:50 PM): "A New Type of Frequency Synthesis for RF and mm-Wave: Charge-Sharin g Locking\," by Dr. Yizhe Hu</strong></p>\n<p style="font-weight: 400\;">< strong>Abstract:</strong></p>\n<p style="font-weight: 400\;">Ultra-low jit ter (sub-100fs) frequency synthesis is highly desirable for 5G RF and mm-W ave (mmW) communications to support the complex modulation schemes (e.g. 1 024QAM). Our group has recently invented a new&nbsp\;<em>charge-sharing lo cking&nbsp\;</em>(CSL) technique to meet these tough requirements. A quadr ature CSL prototype was implemented in TSMC 28nm CMOS and achieves 75fs ji tter in 21.7-to-26.5GHz while consuming only 16.5mW. This talk presents th e details and gives further insights into designing oscillators with ultra -low phase noise in the flicker and thermal regions.</p>\n<h2 style="font- weight: 600\;">Bio:</h2>\n<p style="font-weight: 400\;">Yizhe Hu&nbsp\;rec eived the B.Sc. degree (<em>summa cum laude</em>) in microelectronics from Harbin Institute of Technology (HIT)\, Harbin\, China\, in 2013\, and the PhD degree in microelectronics from University College Dublin (UCD)\, Dub lin\, Ireland\, in 2019. He is currently working as a postdoctoral researc her with Prof. R. Bogdan Staszewski in UCD. From 2013 to 2014\, he was wit h Fudan University\, Shanghai\, China\, where he was involved in RFIC desi gn as a postgraduate researcher. From May 2016 to Oct 2017\, he was consul ting for the PLL Group of HiSilicon\, Huawei Technologies\, China\, design ing 16 nm DCOs and ADPLLs. Since June 2018\, he has been consulting for th e Mixed-Signal Design Department\, TSMC\, for a new type of PLL design. Hi s research interests include RF/mm-wave integrated circuits and systems fo r wireless communications. Dr. Hu has served as a frequent reviewer for th e&nbsp\;<em>IEEE JSSC</em>\,&nbsp\;<em>TCAS</em>-I/II\, and&nbsp\;<em>TMTT </em>.</p>\n<h2 style="font-weight: 600\;">Zoom Broadcast:</h2>\n<p style= "font-weight: 400\;">Lecture will be broadcast live on Zoom and recorded. Please register to receive Zoom conference details one day before the even t.</p>\n<h2 style="font-weight: 600\;">Venue:</h2>\n<p style="font-weight: 400\;"><a href="https://goo.gl/maps/HDvZvuY4Wym">QualComm Santa Clara\, B uilding B\, 3165 Kifer Road\, Santa Clara\, CA 95051</a></p>\n<h2 style="f ont-weight: 600\;">Admission Fee:</h2>\n<p style="font-weight: 400\;">All admissions free. Suggested donations to cover food and water:</p>\n<p styl e="font-weight: 400\;">Non-IEEE: $5\, Students (non-IEEE): $3\, IEEE Membe rs (not members of CASS or SSCS): $3</p>\n<p style="font-weight: 400\;">On line registration is recommended to guarantee seating.</p><br /><br />Agen da: <br /><h2 style="font-weight: 600\;">Advanced Frequency Synthesis For Digitally Intensive Transmitters For IoT And Mm-Wave Radios\, CASS-SCV Mul ti-Speaker Event</h2>\n<h3 style="font-weight: 400\;"><strong>Dr. Robert B ogdan Staszewski\,&nbsp\;School of Electrical &amp\; Electronic Engineerin g\,&nbsp\;</strong><strong>University College Dublin and</strong></h3>\n<h 3 style="font-weight: 400\;"><strong>Dr.&nbsp\;Yizhe Hu\, School of Electr ical &amp\; Electronic Engineering\,&nbsp\;</strong><strong>University Col lege Dublin</strong></h3>\n<h3 style="font-weight: 400\;">Event Organized By:</h3>\n<p style="font-weight: 400\;"><a href="https://site.ieee.org/scv -cas/">Circuits and Systems Society&nbsp\;</a>(CASS-SCV)&nbsp\;of the&nbsp \;<a href="http://sites.ieee.org/scv/">IEEE Santa Clara Valley Section</a> </p>\n<h3 style="font-weight: 400\;">Co-sponsors:</h3>\n<ul style="font-we ight: 400\;">\n<li><a href="http://sites.ieee.org/scv-sscs/upcoming-events /">Solid-State Circuits Society(SSCS)</a></li>\n</ul>\n<ul style="font-wei ght: 400\;">\n<li><a href="https://webinabox.vtools.ieee.org/wibp_home/ind ex/CH06085">Microwave Theory and Techniques (MTT</a>)</li>\n<li><a href="h ttp://www.comsocscv.org/">Communication Society (ComSoc)</a></li>\n<li>\n< h3 style="font-weight: 400\;"><a href="https://ewh.ieee.org/r6/scv/sps/">S ignal Processing Society(SPS)</a></h3>\n</li>\n</ul>\n<p style="font-weigh t: 400\;"><strong>PROGRAM:</strong></p>\n<p>5:30 - 6:00 PM Networking &amp \; Refreshments</p>\n<p>6:00 - 6:50 PM Lecture 1: "Deep-Subthreshold Opera tion of ADPLLs\, Transmitters and ADCs\," by Dr. Robert Bogdan Staszewski< /p>\n<p>6:50 - 7:00 PM Q&amp\;A</p>\n<p>7:00 - 7:50 PM Lecture 2: "A&nbsp\ ;New Type of Frequency Synthesis for RF and mm-Wave: Charge-Sharing Lockin g\," by&nbsp\;Dr. Yizhe Hu</p>\n<p>7:50 - 8:00 PM Q&amp\;A/Adjourn</p>\n<p style="font-weight: 400\;"><strong>Lecture 1 (6:00 - 6:50 PM): "Deep-Subt hreshold Operation of ADPLLs\, Transmitters and ADCs\," by Dr. Robert Bogd an Staszewski</strong></p>\n<p style="font-weight: 400\;"><strong>Abstract :</strong></p>\n<p style="font-weight: 400\;">Internet-of-Things (IoT) dev ices are meant to be powered by energy harvesters\, which unfortunately te nd to generate very little power at very low voltages\, often well below t he threshold voltage of CMOS transistors. Hence the need for an ultra-low power (ULP) and ultra-low voltage (ULV) operation of IoT electronic circui ts. This talk presents recent breakthroughs in collaboration with TSMC in sub-threshold designs of an all-digital PLL (ADPLL)\, RF Bluetooth transmi tter\, and open-loop VCO-based ADC. The supply voltage in these circuits c an go to as low as 0.2V.</p>\n<h2 style="font-weight: 600\;">Bio:</h2>\n<o l start="1995">\n<li style="font-weight: 400\;">Bogdan Staszewskireceived B.Sc. (<em>summa cum laude</em>)\, M.Sc. and PhD from University of Texas at Dallas\, USA\, in 1991\, 1992 and 2002\, respectively. From 1991 to 199 5 he was with Alcatel in Richardson\, Texas. He joined Texas Instruments i n Dallas\, Texas in 1995. In 1999 he co-started a Digital RF Processor (DR P) group in TI with a mission to invent new digitally intensive approaches to traditional RF functions. Dr. Staszewski served as a CTO of the DRP gr oup between 2007 and 2009. In July 2009 he joined Delft University of Tech nology in the Netherlands where he is currently a part-time Full Professor . Since Sept. 2014 he has been a Full Professor at University College Dubl in (UCD) in Ireland. He has co-authored five books\, seven book chapters\, 300 journal and conference publications\, and holds 180 issued US patents . His research interests include nanoscale CMOS architectures and circuits for frequency synthesizers\, transmitters and receivers\, as well as quan tum computers. He is a co-founder of a startup company Equal1 Labs aiming at building the first practical CMOS quantum computer.</li>\n</ol>\n<p sty le="font-weight: 400\;">He is an IEEE Fellow and a recipient of&nbsp\;IEEE Circuits and Systems Industrial Pioneer Award (http://ieee-cas.org/indust rial-pioneer-award-recipients). He was a TPC Chair of IEEE European Solid- State Circuits Conference (ESSCIRC) in 2019 in Krakow\, Poland.</p>\n<p st yle="font-weight: 400\;"><strong>Lecture 2 (7:00 - 7:50 PM): "A New Type o f Frequency Synthesis for RF and mm-Wave: Charge-Sharing Locking\," by Dr. Yizhe Hu</strong></p>\n<p style="font-weight: 400\;"><strong>Abstract:</s trong></p>\n<p style="font-weight: 400\;">Ultra-low jitter (sub-100fs) fre quency synthesis is highly desirable for 5G RF and mm-Wave (mmW) communica tions to support the complex modulation schemes (e.g. 1024QAM). Our group has recently invented a new&nbsp\;<em>charge-sharing locking&nbsp\;</em>(C SL) technique to meet these tough requirements. A quadrature CSL prototype was implemented in TSMC 28nm CMOS and achieves 75fs jitter in 21.7-to-26. 5GHz while consuming only 16.5mW. This talk presents the details and gives further insights into designing oscillators with ultra-low phase noise in the flicker and thermal regions.</p>\n<h2 style="font-weight: 600\;">Bio: </h2>\n<p style="font-weight: 400\;">Yizhe Hu&nbsp\;received the B.Sc. deg ree (<em>summa cum laude</em>) in microelectronics from Harbin Institute o f Technology (HIT)\, Harbin\, China\, in 2013\, and the PhD degree in micr oelectronics from University College Dublin (UCD)\, Dublin\, Ireland\, in 2019. He is currently working as a postdoctoral researcher with Prof. R. B ogdan Staszewski in UCD. From 2013 to 2014\, he was with Fudan University\ , Shanghai\, China\, where he was involved in RFIC design as a postgraduat e researcher. From May 2016 to Oct 2017\, he was consulting for the PLL Gr oup of HiSilicon\, Huawei Technologies\, China\, designing 16 nm DCOs and ADPLLs. Since June 2018\, he has been consulting for the Mixed-Signal Desi gn Department\, TSMC\, for a new type of PLL design. His research interest s include RF/mm-wave integrated circuits and systems for wireless communic ations. Dr. Hu has served as a frequent reviewer for the&nbsp\;<em>IEEE JS SC</em>\,&nbsp\;<em>TCAS</em>-I/II\, and&nbsp\;<em>TMTT</em>.</p>\n<h2 sty le="font-weight: 600\;">Zoom Broadcast:</h2>\n<p style="font-weight: 400\; ">Lecture will be broadcast live on Zoom and recorded. Please register to receive Zoom conference details one day before the event.</p>\n<h2 style=" font-weight: 600\;">Venue:</h2>\n<p style="font-weight: 400\;"><a href="ht tps://goo.gl/maps/HDvZvuY4Wym">QualComm Santa Clara\, Building B\, 3165 Ki fer Road\, Santa Clara\, CA 95051</a></p>\n<h2 style="font-weight: 600\;"> Admission Fee:</h2>\n<p style="font-weight: 400\;">All admissions free. Su ggested donations to cover food and water:</p>\n<p style="font-weight: 400 \;">Non-IEEE: $5\, Students (non-IEEE): $3\, IEEE Members (not members of CASS or SSCS): $3</p>\n<p style="font-weight: 400\;">Online registration i s recommended to guarantee seating.</p> END:VEVENT END:VCALENDAR