BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:Asia/Kolkata
BEGIN:STANDARD
DTSTART:19451014T230000
TZOFFSETFROM:+0630
TZOFFSETTO:+0530
TZNAME:IST
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20200118T074405Z
UID:E032ADAC-289B-4CD0-A78F-CD14558F6AE2
DTSTART;TZID=Asia/Kolkata:20191202T100000
DTEND;TZID=Asia/Kolkata:20191207T170000
DESCRIPTION:Introduction to Hardware description Language followed by Desig
 ning of Combinational circuits with VHDL.\n\nIntroduction to Verilog and D
 igital System Design with Verilog\n\nFPGA Basics\, Synthesis Issue and han
 ds on FPGA Implementation\n\nIntroduction to CMOS VLSI design followed by 
 a session on Modeling of MOS transistor using Spice.\n\nIntroduction to CM
 OS Fabrication Technology and Steps involved in Fabrication process\n\nInf
 ormative session on “Elements of SoC Design with ARM Cortex M0”\,\n\nN
 agpur\, Maharashtra\, India\, 441110
LOCATION:Nagpur\, Maharashtra\, India\, 441110
ORGANIZER:palsodkar.prasanna@ieee.org
SEQUENCE:0
SUMMARY:Six Days Workshop on “Implementation of CMOS VLSI and Digital Sys
 tem Design
URL;VALUE=URI:https://events.vtools.ieee.org/m/218878
X-ALT-DESC:Description: <br /><p>Introduction to Hardware description Langu
 age followed by Designing of Combinational circuits with VHDL. &nbsp\;</p>
 \n<p>Introduction to Verilog and Digital System Design with Verilog</p>\n<
 p>FPGA Basics\, Synthesis Issue and hands on FPGA Implementation</p>\n<p>I
 ntroduction to CMOS VLSI design followed by a session on Modeling of MOS t
 ransistor using Spice.</p>\n<p>Introduction to CMOS Fabrication Technology
  and Steps involved in Fabrication process</p>\n<p>Informative session on 
 &ldquo\;Elements of SoC Design with ARM Cortex M0&rdquo\;\, </p>
END:VEVENT
END:VCALENDAR