BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:US/Eastern
BEGIN:DAYLIGHT
DTSTART:20200308T030000
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3
TZNAME:EDT
END:DAYLIGHT
BEGIN:STANDARD
DTSTART:20201101T010000
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11
TZNAME:EST
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20200514T224120Z
UID:5AE7E2EA-78D5-4173-8D2C-36DEF5AE4B5A
DTSTART;TZID=US/Eastern:20200514T171000
DTEND;TZID=US/Eastern:20200514T180000
DESCRIPTION:In this presentation Dr. Bichan from Intel - Toronto goes over 
 their recent publication at CICC2020 titled "A 32Gb/s NRZ 37dB SerDes in 1
 0nm CMOS to Support PCI Express Gen 5 Protocol". The presentation will be 
 followed by Q&A.\n\nIntroduction: Growing data center bandwidth demand inc
 reases the need for fast wireline transmission. One of the key protocols u
 sed to transfer data between SoC’s is PCI Express. The recently publishe
 d PCI Express Gen 5 standard allows data transmission at up to 32 Gb/s. Th
 e practical design requirements for a PCI Express Gen 5 PHY IP go beyond p
 rotocol compliance. Other considerations include: small IP area\, die-edge
  dimension\, and power to allow large numbers of data links in a single So
 C\, large dynamic temperature range for extreme environmental conditions\,
  advanced power management to reduce power when the link is not in use\, l
 ow data path latency to improve overall system performance\, and robust pe
 rformance with internal adaptive equalization. This paper presents the fir
 st SerDes design to demonstrate a PCI Express 5 link with area of 0.33mm2 
 per lane\, die edge usage per lane of 285um\, dynamic junction temperature
  range from -40C to 125C\, energy efficiency of 11.4pJ/bit including PLL a
 nd clocking\, power management including power gating for all analog block
 s\, continuous data rate support between 1-32Gb/s\, and supporting channel
  topologies with insertion loss up to 37dB at 16GHz with BER < 1e-12 in 10
 nm process technology.\n\nSpeaker(s): Mike Bichan\, \n\nToronto\, Ontario\
 , Canada
LOCATION:Toronto\, Ontario\, Canada
ORGANIZER:alireza.sharif-bakhtiar@ieee.org
SEQUENCE:2
SUMMARY:A 32Gb/s NRZ 37dB SerDes in 10nm CMOS to Support PCI Express Gen 5 
 Protocol
URL;VALUE=URI:https://events.vtools.ieee.org/m/230243
X-ALT-DESC:Description: <br /><p>In this presentation Dr. Bichan from Intel
  - Toronto goes over their recent publication at CICC2020 titled "A 32Gb/s
  NRZ 37dB SerDes in 10nm CMOS to Support PCI Express Gen 5 Protocol". The 
 presentation will be followed by Q&amp\;A.&nbsp\;&nbsp\;</p>\n<p>Introduct
 ion: Growing data center bandwidth demand increases the need for fast wire
 line transmission. One of the key protocols used to transfer data between 
 SoC&rsquo\;s is PCI Express. The recently published PCI Express Gen 5 stan
 dard allows data transmission at up to 32 Gb/s. The practical design requi
 rements for a PCI Express Gen 5 PHY IP go beyond protocol compliance. Othe
 r considerations include: small IP area\, die-edge dimension\, and power t
 o allow large numbers of data links in a single SoC\, large dynamic temper
 ature range for extreme environmental conditions\, advanced power manageme
 nt to reduce power when the link is not in use\, low data path latency to 
 improve overall system performance\, and robust performance with internal 
 adaptive equalization. This paper presents the first SerDes design to demo
 nstrate a PCI Express 5 link with area of 0.33mm2 per lane\, die edge usag
 e per lane of 285um\, dynamic junction temperature range from -40C to 125C
 \, energy efficiency of 11.4pJ/bit including PLL and clocking\, power mana
 gement including power gating for all analog blocks\, continuous data rate
  support between 1-32Gb/s\, and supporting channel topologies with inserti
 on loss up to 37dB at 16GHz with BER &lt\; 1e-12 in 10nm process technolog
 y.</p>
END:VEVENT
END:VCALENDAR