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PRODID:IEEE vTools.Events//EN
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DTSTART:20200308T030000
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DTSTART:20201101T010000
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DTSTAMP:20200730T174616Z
UID:3310293A-C377-4C70-ABD0-C2D6A76F6139
DTSTART;TZID=America/Los_Angeles:20200710T100000
DTEND;TZID=America/Los_Angeles:20200710T113000
DESCRIPTION:Data rates in high-speed wireline communication links continue 
 to increase\, fueled by demands in data center and high-performance comput
 ing applications. In recent years\, serial link data rates have increased 
 from 28Gb/s to 56Gb/s\, with 112Gb/s rapidly approaching. To achieve these
  higher data rates across high-loss electrical channels\, standards are sw
 itching from NRZ to PAM4 signaling. In this talk\, we will start with an o
 verview of serial transmitter architectures focusing on feed-forward equal
 ization (FFE) techniques as well as power considerations for PAM4 links. N
 ext\, we will look at the design of a 56-Gb/s PAM4 transmitter designed in
  14nm FinFET CMOS technology with a fractionally-spaced FFE. Finally\, we 
 will look at directions for 112Gb/s and discuss the design of a 112-Gb/s P
 AM4 transmitter in 14nm FinFET CMOS technology with precise equalization c
 ontrol to minimize intersymbol interference in PAM4 links.\n\nSpeaker(s): 
 DR. Timothy (Tod)  DICKSON\, \n\nSan Diego\, California\, United States
LOCATION:San Diego\, California\, United States
ORGANIZER:alvin.loke@alumni.stanford.edu
SEQUENCE:2
SUMMARY:High-Speed CMOS Serial Transmitters for 56-112Gb/s Electrical Inter
 connects
URL;VALUE=URI:https://events.vtools.ieee.org/m/234033
X-ALT-DESC:Description: <br /><p>Data rates in high-speed wireline communic
 ation links continue to increase\, fueled by demands in data center and hi
 gh-performance computing applications.&nbsp\; In recent years\, serial lin
 k data rates have increased from 28Gb/s to 56Gb/s\, with 112Gb/s rapidly a
 pproaching.&nbsp\; To achieve these higher data rates across high-loss ele
 ctrical channels\, standards are switching from NRZ to PAM4 signaling.&nbs
 p\; In this talk\, we will start with an overview of serial transmitter ar
 chitectures focusing on feed-forward equalization (FFE) techniques as well
  as power considerations for PAM4 links.&nbsp\; Next\, we will look at the
  design of a 56-Gb/s PAM4 transmitter designed in 14nm FinFET CMOS technol
 ogy with a fractionally-spaced FFE.&nbsp\; Finally\, we will look at direc
 tions for 112Gb/s and discuss the design of a 112-Gb/s PAM4 transmitter in
  14nm FinFET CMOS technology with precise equalization control to minimize
  intersymbol interference in PAM4 links.</p>
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