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DTSTART:20210314T030000
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DTSTAMP:20201120T211023Z
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DTSTART;TZID=America/New_York:20201119T200000
DTEND;TZID=America/New_York:20201119T213000
DESCRIPTION:How will computing power increase in the future? We need to use
  parallelism more effectively.\n\nInnovative parallel system designs like 
 GPUs and the TPU have achieved significant performance improvements. Howev
 er\, a closer look will reveal that these gains have largely been achieved
  on “dense” computations\, in which data is accessed in regular\, pred
 ictable patterns. But we also need to achieve improvements in “sparse”
  graph computations\, because these computations are a natural way to repr
 esent and analyze important data structures\, such as social networks and 
 consumer behaviors.\n\nThis talk will present some of the current work at 
 Princeton on parallel heterogeneous systems – and how to use them to acc
 elerate graph applications. One part of this effort has aimed at optimizin
 g graph applications for a prevalent existing system: the CPU/GPU SoC. A d
 omain specific language and an optimizing compiler have been created to co
 nduct a large empirical study on a range of GPU systems. This talk will pr
 esent some key results of the study\, including significant speedups\, hor
 rible slowdowns\, and a new robust definition of performance portability.\
 n\nAnother part of the research program is the design of a new parallel he
 terogeneous architecture\, with reconfigurable and programmable communicat
 ion structures tailored for graph computations. This system addresses key 
 memory bottlenecks by pairing up the simple cores of a many-core system in
  a producer/consumer relationship. Simulation results show that our design
  is significantly more efficient (up to 20x) than existing processors.\n\n
 Speaker(s): Tyler Sorensen\, \n\nVirtual: https://events.vtools.ieee.org/m
 /238138
LOCATION:Virtual: https://events.vtools.ieee.org/m/238138
ORGANIZER:dmancl@acm.org
SEQUENCE:3
SUMMARY:Accelerating Graph Applications on Parallel Heterogeneous Architect
 ures
URL;VALUE=URI:https://events.vtools.ieee.org/m/238138
X-ALT-DESC:Description: <br /><p>How will computing power increase in the f
 uture?&nbsp\; We need to use parallelism more effectively.</p>\n<p>Innovat
 ive parallel system designs like GPUs and the TPU have achieved significan
 t performance improvements.&nbsp\; However\, a closer look will reveal tha
 t these gains have largely been achieved on &ldquo\;dense&rdquo\; computat
 ions\, in which data is accessed in regular\, predictable patterns.&nbsp\;
  But we also need to achieve improvements in &ldquo\;sparse&rdquo\; graph 
 computations\, because these computations are a natural way to represent a
 nd analyze important data structures\, such as social networks and consume
 r behaviors.</p>\n<p>This talk will present some of the current work at Pr
 inceton on parallel heterogeneous systems &ndash\; and how to use them to 
 accelerate graph applications.&nbsp\; One part of this effort has aimed at
  optimizing graph applications for a prevalent existing system: the CPU/GP
 U SoC.&nbsp\; A domain specific language and an optimizing compiler have b
 een created to conduct a large empirical study on a range of GPU systems.&
 nbsp\; This talk will present some key results of the study\, including si
 gnificant speedups\, horrible slowdowns\, and a new robust definition of p
 erformance portability.&nbsp\;</p>\n<p>Another part of the research progra
 m is the design of a new parallel heterogeneous architecture\, with reconf
 igurable and programmable communication structures tailored for graph comp
 utations.&nbsp\; This system addresses key memory bottlenecks by pairing u
 p the simple cores of a many-core system in a producer/consumer relationsh
 ip.&nbsp\; Simulation results show that our design is significantly more e
 fficient (up to 20x) than existing processors.</p>
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