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DESCRIPTION:The 2020 ACM/IEEE International Workshop on System-Level Interc
 onnect Problems and Pathfinding (SLIP^2) is the 22nd\, "rebooted" edition 
 of the System-Level Interconnect Prediction (SLIP) Workshop. As computing 
 systems and applications grapple with a post-Moore\, post-CMOS\, post-von 
 Neumann future\, fundamental interconnect problems and pathfinding challen
 ges have become more critical to address than ever before.\n\nAgenda: \nTE
 CHNICAL TOPICS\n\nTechnical topics include but are not limited to:\n\n- Le
 arning and predictive models for interconnect at various IC and system des
 ign stages\n- Roadmapping and pathfinding of interconnect technology and a
 rchitectures\n- Roadmapping and pathfinding of chip-to-chip interconnect\,
  chiplets\, and chip-package interfaces\n- System-level design for FPGAs\,
  NoCs\, reconfigurable systems\n- 2.5D and 3D-integrated system interconne
 ct optimization\, projection and pathfinding\n- Design\, analysis\, and (c
 o)optimization of power and clock distribution networks\n- Topologies and 
 fabrics of multi- and many-core architectures\n- Predictive models for pow
 er and performance of system-level interconnects\n- Interconnects in socia
 l\, genetic\, and biological systems\n- Interconnects in complex networks 
 and high-performance computing\n- Interconnects in quantum architectures\n
 - System-level interconnect reliability\, aging\, thermal\, yield and cost
  issues\n\n- Bio-inspired connectionist systems\, such as artificial neura
 l networks\n\nVirtual: https://events.vtools.ieee.org/m/239209
LOCATION:Virtual: https://events.vtools.ieee.org/m/239209
ORGANIZER:kathyh@ieee.org
SEQUENCE:1
SUMMARY:2020 ACM/IEEE International Workshop on System-Level Interconnect P
 roblems and Pathfinding (SLIP^2)
URL;VALUE=URI:https://events.vtools.ieee.org/m/239209
X-ALT-DESC:Description: <br /><p>The 2020 ACM/IEEE International Workshop o
 n&nbsp\;<strong>System-Level Interconnect Problems and Pathfinding (SLIP^2
 )</strong>&nbsp\;is the 22nd\, "rebooted" edition of the System-Level Inte
 rconnect Prediction (SLIP) Workshop. As computing systems and applications
  grapple with a post-Moore\, post-CMOS\, post-von Neumann future\, fundame
 ntal interconnect problems and pathfinding challenges have become more cri
 tical to address than ever before.</p><br /><br />Agenda: <br /><div>\n<di
 v>\n<h1>TECHNICAL TOPICS</h1>\n<p><span style="font-family: helvetica\, ar
 ial\, sans-serif\;">Technical topics include but are not limited to:</span
 ></p>\n<ul>\n<li>Learning and predictive models for interconnect at variou
 s IC and system design stages</li>\n<li>Roadmapping and pathfinding of int
 erconnect technology and architectures</li>\n<li>Roadmapping and pathfindi
 ng of chip-to-chip interconnect\, chiplets\, and chip-package interfaces</
 li>\n<li>System-level design for FPGAs\, NoCs\, reconfigurable systems</li
 >\n<li>2.5D and 3D-integrated system interconnect optimization\, projectio
 n and pathfinding</li>\n<li>Design\, analysis\, and (co)optimization of po
 wer and clock distribution networks</li>\n<li>Topologies and fabrics of mu
 lti- and many-core architectures</li>\n<li>Predictive models for power and
  performance of system-level interconnects</li>\n<li>Interconnects in soci
 al\, genetic\, and biological systems</li>\n<li>Interconnects in complex n
 etworks and high-performance computing</li>\n<li>Interconnects in quantum 
 architectures</li>\n<li>System-level interconnect reliability\, aging\, th
 ermal\, yield and cost issues</li>\n</ul>\n<ul>\n<li><span style="font-fam
 ily: helvetica\, arial\, sans-serif\;">Bio-inspired connectionist systems\
 , such as artificial neural networks</span></li>\n</ul>\n<br /><br />&nbsp
 \;&nbsp\; &nbsp\;&nbsp\;</div>\n<div><iframe id="twitter-widget-0" class="
 twitter-timeline twitter-timeline-rendered" title="Twitter Timeline" frame
 border="0" scrolling="no" allowfullscreen="true" data-widget-id="profile:S
 LIPPWorkshop"></iframe></div>\n</div>
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