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DTSTART:20210314T030000
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DTSTART:20201101T010000
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DTSTAMP:20201203T134607Z
UID:196FCE56-7623-4714-832A-43DDD1F13B9C
DTSTART;TZID=Canada/Eastern:20201126T180000
DTEND;TZID=Canada/Eastern:20201126T210000
DESCRIPTION:Security has become a critical design challenge for modern elec
 tronic hardware. With the emergence of the Internet of Things (IoT) regime
  that promises exciting new applications from smart cities to connected au
 tonomous vehicles\, security has come to the forefront of the system-desig
 n process. Recent discoveries and reports on numerous security attacks on 
 microchips and circuits violate the well-regarded concept of hardware trus
 t anchors. It has prompted system designers to develop a wide array of des
 ign-for-security and test/validation solutions to achieve high-security as
 surance for electronic hardware\, which supports the software stack. At th
 e same time\, emerging security issues and countermeasures have also led t
 o interesting interplay between security\, verification and interoperabili
 ty. Verification of hardware for security and trust at different levels of
  abstraction is rapidly becoming an integral part of the system design flo
 w. The global economic trend that promotes outsourcing of design and fabri
 cation process to untrusted facilities coupled with the prevalent practice
  of system on chip design using untrusted third-party intellectual propert
 y blocks (IPs)\, has given rise to the critical need of trust verification
  of IPs\, system-on-chip design\, and fabricated chips.\n\nThe talk will a
 lso cover a spectrum of security challenges for IoTs and describe emerging
  solutions in creating secure trustworthy hardware that can enable IoT sec
 urity for the mass.\n\nSpeaker(s): Swarup Bhunia\, \n\nAgenda: \n6:00 PM -
 -- Virtual Registration and welcome remarks by session chair and vice chai
 r\n\n6:20 PM --- Technical Session\n\n8:20 PM --- Q &amp; A\n\n8:50 PM --- Clo
 sing\n\nVirtual: https://events.vtools.ieee.org/m/240161
LOCATION:Virtual: https://events.vtools.ieee.org/m/240161
ORGANIZER:y.abbas@ieee.org
SEQUENCE:13
SUMMARY:Security of the Internet of Things (IoT): Are We Paranoid Enough?
URL;VALUE=URI:https://events.vtools.ieee.org/m/240161
X-ALT-DESC:Description: &lt;br /&gt;&lt;p&gt;Security has become a critical design chal
 lenge for modern electronic hardware. With the emergence of the Internet o
 f Things (IoT) regime that promises exciting new applications from smart c
 ities to connected autonomous vehicles\, security has come to the forefron
 t of the system-design process. Recent discoveries and reports on numerous
  security attacks on microchips and circuits violate the well-regarded con
 cept of hardware trust anchors. It has prompted system designers to develo
 p a wide array of design-for-security and test/validation solutions to ach
 ieve high-security assurance for electronic hardware\, which supports the 
 software stack. At the same time\, emerging security issues and countermea
 sures have also led to interesting interplay between security\, verificati
 on and interoperability. Verification of hardware for security and trust a
 t different levels of abstraction is rapidly becoming an integral part of 
 the system design flow. The global economic trend that promotes outsourcin
 g of design and fabrication process to untrusted facilities coupled with t
 he prevalent practice of system on chip design using untrusted third-party
  intellectual property blocks (IPs)\, has given rise to the critical need 
 of trust verification of IPs\, system-on-chip design\, and fabricated chip
 s.&lt;/p&gt;\n&lt;p&gt;The talk will also cover a spectrum of security challenges for 
 IoTs and describe emerging solutions in creating secure trustworthy hardwa
 re that can enable IoT security&amp;nbsp\;for the mass.&lt;/p&gt;&lt;br /&gt;&lt;br /&gt;Agenda:
  &lt;br /&gt;&lt;p&gt;6:00 PM --- Virtual Registration and welcome remarks by session 
 chair and vice chair&lt;/p&gt;\n&lt;p&gt;6:20 PM --- Technical Session&amp;nbsp\;&lt;/p&gt;\n&lt;p&gt;
 8:20 PM --- Q &amp;amp\; A&lt;/p&gt;\n&lt;p&gt;8:50 PM --- Closing&lt;/p&gt;
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