BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:Asia/Kolkata
BEGIN:STANDARD
DTSTART:19451014T230000
TZOFFSETFROM:+0630
TZOFFSETTO:+0530
TZNAME:IST
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20200930T112913Z
UID:BD391729-963F-48F8-A7A5-31687710F64F
DTSTART;TZID=Asia/Kolkata:20200617T110000
DTEND;TZID=Asia/Kolkata:20200617T130000
DESCRIPTION:The entire design flow of ASIC and FPGA was thoroughly explaine
 d in this lecture by Mr K Naresh\, Assistant Professor\, Dept. of ECE\, VN
 RVJIET.\n\nThe session started with the constraints and features one looks
  for while designing and manufacturing a chip few of which are cost\, desi
 gn time\, component supply\, prior experience\, training\, power source\, 
 power consumption\, rapid prototyping\, etc.\n\nClassification and Compari
 son of VLSI CAD Tools was done\, and step by step process was explained.\n
 \nThe meaning of technology and the actual meaning of channel length was e
 xplained\, also the current technology was talked about.\n\nDifferent tool
 s which can be used for succesfully finishing a design flow was throwed li
 ght upon.\n\nSpeaker(s): Mr K Naresh\, \n\nAgenda: \nThe main aim of condu
 cting this lecture was to familiarize the students with the ASIC &amp; FPGA De
 sign flow and build a strong understanding of the technical terms in the s
 ame process.\n\nHyderabad\, Andhra Pradesh\, India
LOCATION:Hyderabad\, Andhra Pradesh\, India
ORGANIZER:tharunkumar@ieee.org
SEQUENCE:0
SUMMARY:Lecture on &quot;VLSI Design Flow (FPGA &amp; ASIC)&quot;
URL;VALUE=URI:https://events.vtools.ieee.org/m/241645
X-ALT-DESC:Description: &lt;br /&gt;&lt;p&gt;The entire design flow of ASIC and FPGA wa
 s thoroughly explained in this lecture by Mr K Naresh\, Assistant Professo
 r\, Dept. of ECE\, VNRVJIET.&lt;/p&gt;\n&lt;p&gt;The session started with the constrai
 nts and features one looks for while designing and manufacturing a chip fe
 w of which are cost\, design time\, component supply\, prior experience\, 
 training\, power source\, power consumption\, rapid prototyping\, etc.&lt;/p&gt;
 \n&lt;p&gt;Classification and Comparison of VLSI CAD Tools was done\, and step b
 y step process was explained.&lt;/p&gt;\n&lt;p&gt;The meaning of technology and the ac
 tual meaning of channel length was explained\, also the current technology
  was talked about.&lt;/p&gt;\n&lt;p&gt;Different tools which can be used for succesful
 ly finishing a design flow was throwed light upon.&lt;/p&gt;&lt;br /&gt;&lt;br /&gt;Agenda: 
 &lt;br /&gt;&lt;p&gt;The main aim of conducting this lecture was to familiarize the st
 udents with the ASIC &amp;amp\; FPGA Design flow and build a strong understand
 ing of the technical terms in the same process.&lt;/p&gt;
END:VEVENT
END:VCALENDAR