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VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:Asia/Kolkata
BEGIN:STANDARD
DTSTART:19451014T230000
TZOFFSETFROM:+0630
TZOFFSETTO:+0530
TZNAME:IST
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BEGIN:VEVENT
DTSTAMP:20200930T113914Z
UID:01B0AE7A-949F-4BA9-9A44-F39325592680
DTSTART;TZID=Asia/Kolkata:20200618T110000
DTEND;TZID=Asia/Kolkata:20200618T130000
DESCRIPTION:Ms. K Swetha Reddy started the webinar by explaining the studen
 ts the main purpose of Verilog that is to convert the digital circuits int
 o language format in the same way as we develop our applications in C and 
 other programming languages.\n\nThe speaker then explained about the proce
 ss of VLSI design flow which starts from idea to specifications\, design a
 rchitecture\, RTL coding \, RTL verification\, synthesis\, device layout\,
  placement and routing\, mask layout \, foundary which ends at IC chip.\n\
 nHistory and types of HDL (VHDL\, Verilog HDL\, system verilog) were expla
 ined in brief.\n\nThen the speaker showed us the difference between Verilo
 g and VHDL and explained why verilog is better than VHDL in lower level ha
 rdware modeling. It is because Verilog is originally created for modeling 
 and simulating logic gates. And at system level VHDL is better than Verilo
 g.\n\nDesign methodology which is the protocol to design the architecture 
 in HDL language was explained followed by the levels of abstraction which 
 are switch level\, gate level\,data flow level and behavioural level.\n\nT
 hen the session went on to explain about modules and ports\,registers\, de
 lays and operators and a brief information on lexical conventions was give
 n.\n\nAt last\, the speaker gave a recap of all the concepts she covered i
 n the lecture so far and what to expect in the next lecture and ended the 
 session.\n\nSpeaker(s): Ms K Swetha Reddy\, \n\nAgenda: \nThe goal of the 
 lecture was to familiarize the participants with the importance of verilog
  HDL. The main idea was to explain that Verilog allows designers to confid
 e in the design by reducing the chances of failure. Further\, it accelerat
 es simulation which reduces the time-to-market. With all these benefits\, 
 it is impossible for the circuit designers to not use Verilog for hardware
  description and verification.\n\nHyderabad\, Andhra Pradesh\, India
LOCATION:Hyderabad\, Andhra Pradesh\, India
ORGANIZER:tharunkumar@ieee.org
SEQUENCE:0
SUMMARY:Lecture on "Importance of Verilog HDL in Digital Design Automation"
URL;VALUE=URI:https://events.vtools.ieee.org/m/241647
X-ALT-DESC:Description: <br /><p>Ms. K Swetha Reddy started the webinar by 
 explaining the students the main purpose of Verilog that is to convert the
  digital circuits into language format in the same way as we develop our a
 pplications in C and other programming languages.</p>\n<p>The speaker then
  explained about the process of VLSI design flow which starts from idea to
  specifications\, design architecture\, RTL coding \, RTL verification\, s
 ynthesis\, device layout\, placement and routing\, mask layout \, foundary
  which ends at IC chip.</p>\n<p>History and types of HDL (VHDL\, Verilog H
 DL\, system verilog) were explained in brief.</p>\n<p>Then the speaker sho
 wed us the difference between Verilog and VHDL and explained why verilog i
 s better than VHDL in lower level hardware modeling. It is because Verilog
  is originally created for modeling and simulating logic gates. And at sys
 tem level VHDL is better than Verilog.</p>\n<p>Design methodology which is
  the protocol to design the architecture in HDL language was explained fol
 lowed by the levels of abstraction which are switch level\, gate level\,da
 ta flow level and behavioural level.</p>\n<p>Then the session went on to e
 xplain about modules and ports\,registers\, delays and operators and a bri
 ef information on lexical conventions was given.</p>\n<p>At last\, the spe
 aker gave a recap of all the concepts she covered in the lecture so far an
 d what to expect in the next lecture and ended the session.</p><br /><br /
 >Agenda: <br /><p>The goal of the lecture was to familiarize the participa
 nts with the importance of verilog HDL. &nbsp\;The main idea was to explai
 n that Verilog allows designers to confide in the design by reducing the c
 hances of failure. Further\, it accelerates simulation which reduces the t
 ime-to-market. With all these benefits\, it is impossible for the circuit 
 designers to not use Verilog for hardware description and verification.&nb
 sp\;</p>
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