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PRODID:IEEE vTools.Events//EN
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TZID:Asia/Kolkata
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DTSTART:19451014T230000
TZOFFSETFROM:+0630
TZOFFSETTO:+0530
TZNAME:IST
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BEGIN:VEVENT
DTSTAMP:20200930T114905Z
UID:9BA99A12-401A-434B-A7EC-3C5EBC01EE15
DTSTART;TZID=Asia/Kolkata:20200619T110000
DTEND;TZID=Asia/Kolkata:20200619T130000
DESCRIPTION:Mr. K. Naresh started the lecture by explaining the basics\, ty
 pes and preferences of Verilog.\n\nThe speaker explained about the similar
 ities between C and verilog HDL.\n\nThe session proceeded from explaining 
 the differences between continuous assignment and procedural assignment.\n
 \nHe then showed us the types\, their syntaxes and examples of procedural 
 blocks followed by continuing to expand on the topic of procedural assignm
 ents. And gave a detailed explanation on blocking and non blocking assignm
 ents.\n\nMr. Naresh then spoke about advantages and disadvantages race con
 dition.\n\nThe speaker also gave the details on level sensitive timing con
 trol and functions vs tasks and concluded the session by explaining the co
 ncept of regular delay control.\n\nSpeaker(s): M K Naresh\, \n\nAgenda: \n
 This lecture aimed at explaining about behavioral modeling. The basic idea
  is describe how a circuit should behave. For many reasons\, behavioral mo
 deling is considered highest abstraction level as compared to data-flow or
  structural models. The VHDL synthesizer tool decides the actual circuit i
 mplementation.\n\nHyderabad\, Andhra Pradesh\, India
LOCATION:Hyderabad\, Andhra Pradesh\, India
ORGANIZER:tharunkumar@ieee.org
SEQUENCE:0
SUMMARY:Lecture on &quot;Behavior Modelling Style of Verilog HDL&quot;
URL;VALUE=URI:https://events.vtools.ieee.org/m/241649
X-ALT-DESC:Description: &lt;br /&gt;&lt;p&gt;Mr. K. Naresh started the lecture by expla
 ining the basics\, types and preferences of Verilog.&lt;/p&gt;\n&lt;p&gt;The speaker e
 xplained about the similarities between C and verilog HDL.&lt;/p&gt;\n&lt;p&gt;The ses
 sion proceeded from explaining the differences between continuous assignme
 nt and procedural assignment.&lt;/p&gt;\n&lt;p&gt;He then showed us the types\, their 
 syntaxes and examples of procedural blocks followed by continuing to expan
 d on the topic of procedural assignments. And gave a detailed explanation 
 on blocking and non blocking assignments.&lt;/p&gt;\n&lt;p&gt;Mr. Naresh then spoke ab
 out advantages and disadvantages race condition.&lt;/p&gt;\n&lt;p&gt;The speaker also 
 gave the details on level sensitive timing control and functions vs tasks 
 and concluded the session by explaining the concept of regular delay contr
 ol.&lt;/p&gt;&lt;br /&gt;&lt;br /&gt;Agenda: &lt;br /&gt;&lt;p&gt;This lecture aimed at explaining about
  &amp;nbsp\;&lt;strong&gt;behavioral modeling. The basic idea is &lt;/strong&gt;describe h
 ow a circuit should behave. For many reasons\,&amp;nbsp\;&lt;strong&gt;behavioral mo
 deling&lt;/strong&gt;&amp;nbsp\;is considered highest abstraction level as compared 
 to data-flow or structural models. The&amp;nbsp\;&lt;strong&gt;VHDL&lt;/strong&gt;&amp;nbsp\;s
 ynthesizer tool decides the actual circuit implementation.&lt;/p&gt;
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