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PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:Asia/Kolkata
BEGIN:STANDARD
DTSTART:19451014T230000
TZOFFSETFROM:+0630
TZOFFSETTO:+0530
TZNAME:IST
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BEGIN:VEVENT
DTSTAMP:20200930T115600Z
UID:01ED57C5-A0F2-47E0-9335-9F1623B368B4
DTSTART;TZID=Asia/Kolkata:20200622T110000
DTEND;TZID=Asia/Kolkata:20200622T130000
DESCRIPTION:The speaker started the session by giving a brief explanation a
 bout the design of simple electronic circuit.\n\nThen he proceeded by show
 ing us the design of VLSI circuit.\n\nIt was explained that the design of 
 VLSI circuit starts from getting a specification to simplifying that speci
 fication and instead of passing to manual design it goes to CAD (Computer 
 aided design) and from there it goes to simulation followed by synthesis. 
 From there it is passed to gate level net list and layout.\n\nFuther it wa
 s taught that programming will have certain styles like behavioral\, data 
 flow and structural.\n\nThe speaker continued the session that specificati
 ons can be simplified using either truth table or Boolean equation or in t
 erms of logic diagram.\n\nThe speaker showed the process of creating full 
 adder design using the AND gate with the help of tool.\n\nSpeaker(s): Mr C
 h Ganesh\, \n\nAgenda: \nThe goal of the lecture was to familiarize the pa
 rticipants with the basics of verilog HDL and thus explaining us about the
  full adder design using logic gates. The structural modelling style is th
 e lowest level of abstraction obtained using logic gates. Similar to schem
 atic or circuit diagrams of the digital circuit\, Verilog uses primitive g
 ates to compile and synthesize the program. Of course\, this abstraction c
 an&#39;t be understood by humans.\n\nHyderabad\, Andhra Pradesh\, India
LOCATION:Hyderabad\, Andhra Pradesh\, India
ORGANIZER:tharunkumar@ieee.org
SEQUENCE:0
SUMMARY:Lecture on &quot;Structural Modelling Style of Verilog HDL&quot;
URL;VALUE=URI:https://events.vtools.ieee.org/m/241652
X-ALT-DESC:Description: &lt;br /&gt;&lt;p&gt;The speaker started the session by giving 
 a brief explanation about the design of simple electronic circuit.&lt;/p&gt;\n&lt;p
 &gt;Then he proceeded by showing us the design of VLSI circuit.&lt;/p&gt;\n&lt;p&gt;It wa
 s explained that the design of VLSI circuit starts from getting a specific
 ation to simplifying that specification and instead of passing to manual d
 esign it goes to CAD (Computer aided design) and from there it goes to sim
 ulation followed by synthesis. From there it is passed to gate level net l
 ist and layout.&lt;/p&gt;\n&lt;p&gt;Futher it was taught that programming will have ce
 rtain styles like behavioral\, data flow and structural.&lt;/p&gt;\n&lt;p&gt;The speak
 er continued the session that specifications can be simplified using eithe
 r truth table or Boolean equation or in terms of logic diagram.&lt;/p&gt;\n&lt;p&gt;Th
 e speaker showed the process of creating full adder design using the AND g
 ate with the help of tool.&lt;/p&gt;&lt;br /&gt;&lt;br /&gt;Agenda: &lt;br /&gt;&lt;p&gt;The goal of the
  lecture was to familiarize the participants with the basics of verilog HD
 L and thus explaining us about the full adder design using logic gates. Th
 e&amp;nbsp\;&lt;strong&gt;structural modelling&lt;/strong&gt;&amp;nbsp\;style is the lowest le
 vel of abstraction obtained using logic gates. Similar to schematic or cir
 cuit diagrams of the digital circuit\,&amp;nbsp\;&lt;strong&gt;Verilog&lt;/strong&gt;&amp;nbsp
 \;uses primitive gates to compile and synthesize the program. Of course\, 
 this abstraction can&#39;t be understood by humans.&lt;/p&gt;
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