BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:Asia/Kolkata
BEGIN:STANDARD
DTSTART:19451014T230000
TZOFFSETFROM:+0630
TZOFFSETTO:+0530
TZNAME:IST
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20200930T121154Z
UID:F8189D07-EDCA-4E5A-9D06-6BFDF86B2415
DTSTART;TZID=Asia/Kolkata:20200624T110000
DTEND;TZID=Asia/Kolkata:20200624T130000
DESCRIPTION:The session was started by discussing regarding the functionali
 ty design i.e.\, how it should be functionally correct and how to achieve 
 the desired output. Further the speaker talks about how we can generate th
 e test vectors or input combinations to a design so that it can be tested 
 as efficiently as possible. Then\, the advantages of TestBench was explain
 ed and how we can generate values for input combinations. The design of Te
 stBench and the concept of Programming language Interface(PLI) was explain
 ed in detail.\n\nThe speaker also explained about TestBench-Half Adder\, T
 estBench for 2XI MUX and gave related examples about it. Designing of init
 ial block\, how the stimulators work\, how verilog’s compiler will treat
  the statements all these concepts were explained in detail with examples.
 \n\nSpeaker(s): Ms K Swetha Reddy\, \n\nAgenda: \nTo learn regarding the D
 esign Verification of TestBench in Verilog HDL and to check the functional
 ity design. All the concepts were explained clearly and was understood by 
 the students.\n\nHyderabad\, Andhra Pradesh\, India
LOCATION:Hyderabad\, Andhra Pradesh\, India
ORGANIZER:tharunkumar@ieee.org
SEQUENCE:0
SUMMARY:Lecture on &quot;Design Verification Using TestBench&quot;
URL;VALUE=URI:https://events.vtools.ieee.org/m/241654
X-ALT-DESC:Description: &lt;br /&gt;&lt;p&gt;The session was started by discussing rega
 rding the functionality design i.e.\, how it should be functionally correc
 t and how to achieve the desired output. Further the speaker talks about h
 ow we can generate the test vectors or input combinations to a design so t
 hat it can be tested as efficiently as possible. Then\, the advantages of 
 TestBench was explained and how we can generate values for input combinati
 ons. The design of TestBench and the concept of Programming language Inter
 face(PLI) was explained in detail.&lt;/p&gt;\n&lt;p&gt;The speaker also explained abou
 t TestBench-Half Adder\, TestBench for 2XI MUX and gave related examples a
 bout it. Designing of initial block\, how the stimulators work\, how veril
 og&amp;rsquo\;s compiler will treat the statements all these concepts were exp
 lained in detail with examples.&lt;/p&gt;&lt;br /&gt;&lt;br /&gt;Agenda: &lt;br /&gt;&lt;p&gt;To learn r
 egarding the Design Verification of TestBench in Verilog HDL and to check 
 the functionality design. All the concepts were explained clearly and was 
 understood by the students.&lt;/p&gt;
END:VEVENT
END:VCALENDAR