BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:Canada/Eastern
BEGIN:DAYLIGHT
DTSTART:20210314T030000
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3
TZNAME:EDT
END:DAYLIGHT
BEGIN:STANDARD
DTSTART:20201101T010000
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11
TZNAME:EST
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20210119T045027Z
UID:7D074E64-9F3E-4A45-95D4-A5BD73A11ABC
DTSTART;TZID=Canada/Eastern:20201117T150000
DTEND;TZID=Canada/Eastern:20201117T163000
DESCRIPTION:Memory technology is a defining component of modern computing a
 nd has a strong impact on performance\, power and cost of computing system
 s. However\, the advances in memory performance have not been able to keep
  up with the performance advances for CPU’s\, thus leading to what is kn
 own as “the memory wall.” Depending on the application\, the memory wa
 ll manifests itself both in terms of memory latency\, as well as memory ba
 ndwidth. An interesting solution to the memory wall problem is to bring me
 mory closer to the processor\, or vice-versa\, to move some processing cap
 ability in the memory itself – this leads to variations of what is known
  as Near-Memory Processing\, Processing in Memory (PiM)\, etc. This semina
 r will first introduce a PIM taxonomy along several dimensions of the PiM 
 design space\; it will then follow with a history of PIM\, then go over se
 veral recent PIM examples. The seminar will then go in depth into the Ther
 mal/Power delivery challenges for PIM that are a result of the increased s
 witching activities inherent to the moving of processing into the memory f
 abric\, and exacerbated by the evolution towards 3D integration due to the
  slow-down of traditional Moore’s law methods. The seminar will conclude
  with some novel solutions that alleviate the Thermal/Power challenges for
  PiM.\n\nCo-sponsored by: Microsystems Strategic Alliance of Québec (ReSM
 iQ)\n\nSpeaker(s): Mircea Stan\, \n\nVirtual: https://events.vtools.ieee.o
 rg/m/244014
LOCATION:Virtual: https://events.vtools.ieee.org/m/244014
ORGANIZER:benoit.gosselin@gel.ulaval.ca
SEQUENCE:4
SUMMARY:Séminaires Séminaire IEEE CAS - ReSMiQ le 17 novembre à 15h00 vi
 a WebEx: Processing in Memory (PIM) – Power and Thermal Challenges and O
 pportunities
URL;VALUE=URI:https://events.vtools.ieee.org/m/244014
X-ALT-DESC:Description: <br /><p>Memory technology is a defining component 
 of modern computing and has a strong impact on performance\, power and cos
 t of computing systems. However\, the advances in memory performance have 
 not been able to keep up with the performance advances for CPU&rsquo\;s\, 
 thus leading to what is known as &ldquo\;the memory wall.&rdquo\; Dependin
 g on the application\, the memory wall manifests itself both in terms of m
 emory latency\, as well as memory bandwidth. An interesting solution to th
 e memory wall problem is to bring memory closer to the processor\, or vice
 -versa\, to move some processing capability in the memory itself &ndash\; 
 this leads to variations of what is known as Near-Memory Processing\, Proc
 essing in Memory (PiM)\, etc. This seminar will first introduce a PIM taxo
 nomy along several dimensions of the PiM design space\; it will then follo
 w with a history of PIM\, then go over several recent PIM examples. The se
 minar will then go in depth into the Thermal/Power delivery challenges for
  PIM that are a result of the increased switching activities inherent to t
 he moving of processing into the memory fabric\, and exacerbated by the ev
 olution towards 3D integration due to the slow-down of traditional Moore&r
 squo\;s law methods. The seminar will conclude with some novel solutions t
 hat alleviate the Thermal/Power challenges for PiM.</p>
END:VEVENT
END:VCALENDAR