BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Edmonton BEGIN:DAYLIGHT DTSTART:20210314T030000 TZOFFSETFROM:-0700 TZOFFSETTO:-0600 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:MDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20201101T010000 TZOFFSETFROM:-0600 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:MST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20210301T192328Z UID:94B32D36-9242-4252-BCD3-1F5129C64352 DTSTART;TZID=America/Edmonton:20201112T120000 DTEND;TZID=America/Edmonton:20201112T130000 DESCRIPTION:For decades there has been a new CMOS technology node approxima tely every two years. Until recently\, thanks to scaling\, the key feature of every new technology node has been a 100% integration capacity and 40% performance improvement… free-of-charge. The International Technology R oadmap for Semiconductors (ITRS) has been architected in such a way that t his improvement became a self-fulfilling prophecy of the roadmap itself. E verything else has been bent in the attempt to make scaling happen… fore ver. That has changed as we approach the near end of Moore’s Law.\n\nFor eons snails have built the cells of their shell according to the Fibonacc i’s numbers – where each cell has a volume that is the sum of the volu me of the previous two cells. Snails understand\, however\, that at a cert ain point in time growth must stop to prevent the collapse of the shell by making it too big and therefore fragile. When this point is reached\, sna ils do stop adding larger cells\, and start improving the robustness of th e shell.\n\nBack to us: technology-wise\, scaling has rapidly exhausted th e resources of CMOS technology\, which\, by now\, struggles to deliver any further improvement. A number of fundamental challenges have emerged\, bo th technical and financial\, which force a thorough rethinking of how scal ing has been done\, and whether scaling continues to be the most appropria te solution to provide the world with the silicon content that it needs.\n \nLike Al Gore’s premise on energy consumption and global warming\, ther e is an inconvenient truth to be acknowledged in our industry: scaling is like fossil fuels – the cheapest and easiest way to go. Unfortunately\, also like fossil fuels\, it is not sustainable indefinitely. And it become s more costly and inefficient every day. New avenues\, which are available today\, are worth exploring and must be undertaken. That is\, unless snai ls are more intelligent than us…\n\nIn this talk\, Dr. Williams will des cribe the problems with scaling and a number of possible solutions\, inclu ding the latest alternative paths and their relative merits.\n\n---------- -------------------------------------------------------------------------- -------------------------------------------------------------------------- -----\n\nDr. Thomas W. Williams is a retired Synopsys Fellow at Synopsys i n Boulder\, Colorado\, U.S.A\, currently living in Canmore\, AB\, Canada. Formerly\, he was with IBM Microelectronics Division and manager of the VL SI Design for Testability group. He received a B.S.E.E. from Clarkson Univ ersity\, an M.A. in pure mathematics from the State University of New York at Binghamton\, and a Ph.D. in electrical engineering from Colorado State University. Dr. Williams was named an IEEE Fellow in 1988 and received th e Computer Society's W. Wallace McDowell Award for outstanding contributio ns to the computer art in 1989. In 2018 he received the Phil Kaufman Award \, “The Nobel Prize” of Semiconductor Industry.\n\nVirtual: https://ev ents.vtools.ieee.org/m/244887 LOCATION:Virtual: https://events.vtools.ieee.org/m/244887 ORGANIZER:ladawson@ucalgary.ca SEQUENCE:8 SUMMARY:Another Inconvenient Truth: Snails Are More Intelligent Than Us URL;VALUE=URI:https://events.vtools.ieee.org/m/244887 X-ALT-DESC:Description: <br /><p>For decades there has been a new CMOS tech nology node approximately every two years. Until recently\, thanks to scal ing\, the key feature of every new technology node has been a 100% integra tion capacity and 40% performance improvement&hellip\; free-of-charge. The International Technology Roadmap for Semiconductors (ITRS) has been archi tected in such a way that this improvement became a self-fulfilling prophe cy of the roadmap itself. Everything else has been bent in the attempt to make scaling happen&hellip\; forever. That has changed as we approach the near end of Moore&rsquo\;s Law.&nbsp\;</p>\n<p>For eons snails have built the cells of their shell according to the Fibonacci&rsquo\;s numbers &ndas h\; where each cell has a volume that is the sum of the volume of the prev ious two cells. Snails understand\, however\, that at a certain point in t ime growth must stop to prevent the collapse of the shell by making it too big and therefore fragile. When this point is reached\, snails do stop ad ding larger cells\, and start improving the robustness of the shell.</p>\n <p>Back to us: technology-wise\, scaling has rapidly exhausted the resourc es of CMOS technology\, which\, by now\, struggles to deliver any further improvement.&nbsp\;A number of fundamental challenges have emerged\, both technical and financial\, which force a thorough rethinking of how scaling has been done\, and whether scaling continues to be the most appropriate solution to provide the world with the silicon content that it needs.</p>\ n<p>Like Al Gore&rsquo\;s premise on energy consumption and global warming \, there is an inconvenient truth to be acknowledged in our industry: scal ing is like fossil fuels &ndash\; the cheapest and easiest way to go. Unfo rtunately\, also like fossil fuels\, it is not sustainable indefinitely. A nd it becomes more costly and inefficient every day. New avenues\, which a re available today\, are worth exploring and must be undertaken. That is\, unless snails are more intelligent than us&hellip\;</p>\n<p>In this talk\ , Dr. Williams will describe the problems with scaling and a number of pos sible solutions\, including the latest alternative paths and their relativ e merits.</p>\n<p>-------------------------------------------------------- -------------------------------------------------------------------------- ---------------------------------</p>\n<p>Dr. Thomas W. Williams is a reti red Synopsys Fellow at Synopsys in Boulder\, Colorado\, U.S.A\, currently living in Canmore\, AB\, Canada. Formerly\, he was with IBM Microelectroni cs Division and manager of the VLSI Design for Testability group. He recei ved a B.S.E.E. from Clarkson University\, an M.A. in pure mathematics from the State University of New York at Binghamton\, and a Ph.D. in electrica l engineering from Colorado State University. Dr. Williams was named an IE EE Fellow in 1988 and received the Computer Society's W. Wallace McDowell Award for outstanding contributions to the computer art in 1989. In 2018 h e received the Phil Kaufman Award\, &ldquo\;The Nobel Prize&rdquo\; of Sem iconductor Industry.</p> END:VEVENT END:VCALENDAR