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DTSTART:20210314T030000
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DTSTART:20201101T010000
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BEGIN:VEVENT
DTSTAMP:20201102T034517Z
UID:50742809-18AB-4B79-9C09-B7A240242183
DTSTART;TZID=US/Eastern:20201123T163000
DTEND;TZID=US/Eastern:20201123T173000
DESCRIPTION:Abstract: Data rates in high-speed wireline communication links
  continue to increase\, fueled by demands in\ndata center and high-perform
 ance computing applications. In recent years\, serial link data rates have
 \nincreased from 28Gb/s to 56Gb/s\, with 112Gb/s rapidly approaching. To a
 chieve these higher data rates\nacross high-loss electrical channels\, sta
 ndards are switching from NRZ to PAM4 signaling. In this talk\, we\nwill s
 tart with an overview of serial transmitter architectures focusing on feed
 -forward equalization (FFE)\ntechniques as well as power considerations fo
 r PAM4 links. Next\, we will look at the design of a 56-Gb/s\nPAM4 transmi
 tter designed in 14nm FinFET CMOS technology with a fractionally-spaced FF
 E. Finally we\nwill look at directions for 112Gb/s and discuss the design 
 of a 112-Gb/s PAM4 transmitter in 14nm FinFET\nCMOS technology with precis
 e equalization control to minimize intersymbol interference in PAM4 links.
 \n\nSpeaker(s): Timothy O. (Tod) Dickson\, Ph.D.\, \n\nVirtual: https://ev
 ents.vtools.ieee.org/m/246808
LOCATION:Virtual: https://events.vtools.ieee.org/m/246808
ORGANIZER:shubha.bpallya@gmail.com
SEQUENCE:2
SUMMARY:High-Speed CMOS Serial Transmitters for 56-112Gb/s Electrical Inter
 connects 
URL;VALUE=URI:https://events.vtools.ieee.org/m/246808
X-ALT-DESC:Description: <br /><p>Abstract: Data rates in high-speed wirelin
 e communication links continue to increase\, fueled by demands in<br />dat
 a center and high-performance computing applications. In recent years\, se
 rial link data rates have<br />increased from 28Gb/s to 56Gb/s\, with 112G
 b/s rapidly approaching. To achieve these higher data rates<br />across hi
 gh-loss electrical channels\, standards are switching from NRZ to PAM4 sig
 naling. In this talk\, we<br />will start with an overview of serial trans
 mitter architectures focusing on feed-forward equalization (FFE)<br />tech
 niques as well as power considerations for PAM4 links. Next\, we will look
  at the design of a 56-Gb/s<br />PAM4 transmitter designed in 14nm FinFET 
 CMOS technology with a fractionally-spaced FFE. Finally we<br />will look 
 at directions for 112Gb/s and discuss the design of a 112-Gb/s PAM4 transm
 itter in 14nm FinFET<br />CMOS technology with precise equalization contro
 l to minimize intersymbol interference in PAM4 links.</p>
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