BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:US/Eastern BEGIN:DAYLIGHT DTSTART:20210314T030000 TZOFFSETFROM:-0500 TZOFFSETTO:-0400 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:EDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20201101T010000 TZOFFSETFROM:-0400 TZOFFSETTO:-0500 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:EST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20210122T000249Z UID:074BF398-0AFA-4A6E-9B1D-B255CEC0AC4B DTSTART;TZID=US/Eastern:20210121T120000 DTEND;TZID=US/Eastern:20210121T130000 DESCRIPTION:Ever since the proposal and demonstration of quantum dots in 19 80 by Efros’ brothers and Dr. Ekimov\, the relentless progress of nanote chnology has been unstoppable. And nowhere this progress is more evident a s in the Si Very Large Scale Integrated Circuits (VLSI) technology. The mi nimum feature sizes of the Si VLSI reduced to 7 nm in 2017 with plans for the 5 nm and even 3 nm technology. With over 20 billion transistors on a s quare cm chip in 2018 and the expectations of reaching 1 trillion transist ors on chip in the near future\, the complexity of the VLSI\nfabrication p rocesses and the commensurate costs are overwhelming. The quality of the c rystalline silicon becomes crucial to guarantee an acceptable yield\, and the device physics involved is new and counter-intuitive. But industrial s ilicon nanotechnology is not limited to crystalline materials. Amorphous a nd polysilicon Thin Film Transistors fabricated on glass or even on cloth or paper enable integrated circuits with 50 nm tolerances over square mete r sizes. These technologies have become disruptive with applications rangi ng from entertainment to communications dubbed 5G and Beyond 5G\, to robot ics and driverless cars\, and to the new electronic and communication warf are. This talk will focus on the Computer Aided Design compact models requ ired to support the design\, characterization\, and parameter extraction f or Si VLSI and a-Si and polysilicon integrated circuits\, and on the new p atent pending VLSI test techniques needed to identify and diagnose bad or faked VLSI chips.\n\nCo-sponsored by: Baltimore Section Jt Chapter\, ED15/ SSC37 \n\nSpeaker(s): Prof. Michael Shur\, \n\nVirtual: https://events.vto ols.ieee.org/m/247990 LOCATION:Virtual: https://events.vtools.ieee.org/m/247990 ORGANIZER:tonyguo@ieee.org SEQUENCE:15 SUMMARY:State-of-the-Art Silicon Very Large Scale Integrated Circuits: Indu strial Face of Nanotechnology URL;VALUE=URI:https://events.vtools.ieee.org/m/247990 X-ALT-DESC:Description: <br /><p>Ever since the proposal and demonstration of quantum dots in 1980 by Efros&rsquo\; brothers and Dr. Ekimov\, the rel entless progress of nanotechnology has been unstoppable. And nowhere this progress is more evident as in the Si Very Large&nbsp\;Scale Integrated Ci rcuits (VLSI) technology. The minimum feature sizes of the Si&nbsp\;VLSI r educed to 7 nm in 2017 with plans for the 5 nm and even 3 nm technology.&n bsp\;With over 20 billion transistors on a square cm chip in 2018 and the expectations of&nbsp\;reaching 1 trillion transistors on chip in the near future\, the complexity of the VLSI<br />fabrication processes and the com mensurate costs are overwhelming. The quality of&nbsp\;the crystalline sil icon becomes crucial to guarantee an acceptable yield\, and the&nbsp\;devi ce physics involved is new and counter-intuitive. But industrial silicon n anotechnology is not limited to crystalline materials. Amorphous and polys ilicon Thin Film Transistors fabricated on glass or even on cloth or paper enable integrated circuits with 50 nm tolerances over square meter sizes. These technologies have&nbsp\;become disruptive with applications ranging from&nbsp\;entertainment to communications dubbed 5G and Beyond 5G\, to r obotics and&nbsp\;driverless cars\, and to the new electronic and communic ation&nbsp\;warfare. This talk will focus on the Computer Aided Design com pact models&nbsp\;required to support the design\, characterization\, and parameter extraction for Si&nbsp\;VLSI and a-Si and polysilicon integrated circuits\, and on the new patent pending VLSI test techniques needed to i dentify and diagnose bad or faked VLSI chips.</p> END:VEVENT END:VCALENDAR