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DTSTART:20210314T030000
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DTSTAMP:20201208T002648Z
UID:A3A3909B-7DA6-4412-922D-E01939F9FF21
DTSTART;TZID=US/Eastern:20201201T120000
DTEND;TZID=US/Eastern:20201201T133000
DESCRIPTION:Abstract:\n\nFailure of a high-speed integrated circuit (IC) re
 sulting from an electrostatic discharge (ESD) event is one of the main rel
 iability issues in many electronic products. The on-chip protection compon
 ents are area intensive and costly\, so they are typically made to protect
  against the smaller ESD events present during IC handling and not against
  the high-voltage ESD pulses present at the system-level.\n\nIn this webin
 ar\, we will review the main scenarios for ESD risks subjected to high-spe
 ed ICs. Then we will talk about the Transient voltage suppressor (TVS) dio
 des which are installed on high-speed I/O traces to improve system-level E
 SD protection. To protect the circuit\, the majority of ESD current must f
 low into the external TVS diode rather than into the IC\, but due to turn-
 on behavior\, the TVS diode may not snap back when needed and the IC's int
 ernal protection may take most of the current. These race conditions betwe
 en the internal and external ESD protection circuits will be discussed for
  a USB interface board. The results obtained from the measurements and by 
 system efficient ESD design (SEED) simulations will be presented. This web
 inar discusses relevant ESD problems which take extensive precautions for 
 ESD design engineers to become acquainted with them.\n\nSpeaker(s): Dr. Ja
 vad Meiguni of Amazon Lab126\, \n\nMontreal\, Quebec\, Canada\, H5A 1K6\, 
 Virtual: https://events.vtools.ieee.org/m/248885
LOCATION:Montreal\, Quebec\, Canada\, H5A 1K6\, Virtual: https://events.vto
 ols.ieee.org/m/248885
ORGANIZER:mansoor.dashti@gmail.com
SEQUENCE:16
SUMMARY:Advancements in ESD Protection Method and Modeling for High-Speed I
 Cs
URL;VALUE=URI:https://events.vtools.ieee.org/m/248885
X-ALT-DESC:Description: <br /><p style="text-align: justify\;"><span style=
 "font-size: 12pt\;"><strong>&nbsp\;<br />Abstract:</strong></span></p>\n<p
  style="text-align: justify\;"><span style="font-size: 12pt\;">Failure of 
 a high-speed integrated circuit (IC) resulting from an electrostatic disch
 arge (ESD) event is one of the main reliability issues in many electronic 
 products. The on-chip protection components are area intensive and costly\
 , so they are typically made to protect against the smaller ESD events pre
 sent during IC handling and not against the high-voltage ESD pulses presen
 t at the system-level.</span></p>\n<p style="text-align: justify\;"><span 
 style="font-size: 12pt\;">In this webinar\, we will review the main scenar
 ios for ESD risks subjected to high-speed ICs. Then we will talk about the
  Transient voltage suppressor (TVS) diodes which are installed on high-spe
 ed I/O traces to improve system-level ESD protection. To protect the circu
 it\, the majority of ESD current must flow into the external TVS diode rat
 her than into the IC\, but due to turn-on behavior\, the TVS diode may not
  snap back when needed and the IC's internal protection may take most of t
 he current. These race conditions between the internal and external ESD pr
 otection circuits will be discussed for a USB interface board. The results
  obtained from the measurements and by system efficient ESD design (SEED) 
 simulations will be presented. This webinar discusses relevant ESD problem
 s which take extensive precautions for ESD design engineers to become acqu
 ainted with them.</span></p>
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