BEGIN:VCALENDAR
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CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
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DTSTART:20210314T030000
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RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11
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END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20210210T155641Z
UID:DED0BDA4-ECD6-4AA8-89D7-9A953DD699B3
DTSTART;TZID=America/Montreal:20210127T160000
DTEND;TZID=America/Montreal:20210127T170000
DESCRIPTION:When and How\nDate: January 27th\, 2021\nTime: 4:00 pm – 5:00
  pm Eastern Time\nLocation: Saint Maurice\, Trois Rivieres\, Quebec\, CANA
 DA\nZoom: https://uqtr.zoom.us/j/89686450185?pwd=ZWNyLyswa2xsUmRzUmZ3bEFZY
 i9MZz09\nMeeting ID: 896 8645 0185\nPassword: 008577\n\nABSTRACT\n\nThe Ve
 rsal ACAP is a new platform offering from Xilinx that exploits leading edg
 e 7nm semiconductor process technology with semiconductor innovation to cr
 eate a new category of adaptive SoCs. This portfolio of devices can be use
 d to create Domain Specific Architectures that are scalable and optimized 
 to meet a wide range of application requirements from end points to vehicl
 es to infrastructure. 5G architectures requiring compute intensive functio
 nality\, such as massive MIMO and beamforming\, are key target application
 s that are enabled by Versal and its’ silicon innovations.\nTools are a 
 critical component of enabling the developer community to leverage the ful
 l potential of Versal platforms. Vitis Unified Software Platform\, combine
 d with Vivado Design Suite\, offers a comprehensive development environmen
 t and programming model that enables all developers\, including hardware a
 nd software engineers\, and data scientists to access the full potential o
 f Versal ACAP. With Vitis\, developers can meet the growing challenges and
  unique requirements of their applications\, while continuing to work at a
 n application level and develop in familiar programming languages & framew
 orks.\nIn this session\, equal time will be spent reviewing the benefits a
 nd features of both Versal devices and the Vitis tool flow with an emphasi
 s on 5G applications.\n\nSpeaker(s): Ms. Uttara Kumar\, Mr. Josh Sullivan\
 n\n3351 Boulevard des Forges\,\, Trois Rivieres\, Quebec\, Canada\, G9A 5H
 7\, Virtual: https://events.vtools.ieee.org/m/256964
LOCATION:3351 Boulevard des Forges\,\, Trois Rivieres\, Quebec\, Canada\, G
 9A 5H7\, Virtual: https://events.vtools.ieee.org/m/256964
ORGANIZER:messaoud.ahmed.ouameur@uqtr.ca
SEQUENCE:6
SUMMARY:THE VERSAL ACAP XILINX’S NEW PLATFORM USING LEADING EDGE 7NM SEMI
 CONDUCTOR PROCESS TECHNOLOGY
URL;VALUE=URI:https://events.vtools.ieee.org/m/256964
X-ALT-DESC:Description: <br /><p><span style="background-color: #ffffff\;">
 <strong>When and How</strong><br /><strong>Date:</strong> January 27th\, 2
 021<br /><strong>Time:</strong> 4:00 pm &ndash\; 5:00 pm Eastern Time<br /
 ><strong>Location:</strong> Saint Maurice\, Trois Rivieres\, Quebec\, CANA
 DA<br /><strong>Zoom:</strong> https://uqtr.zoom.us/j/89686450185?pwd=ZWNy
 Lyswa2xsUmRzUmZ3bEFZYi9MZz09 <br /><strong>Meeting ID:</strong> 896 8645 0
 185 <br /><strong>Password:</strong> 008577</span></p>\n<p><strong><span s
 tyle="background-color: #ffffff\;">ABSTRACT</span></strong></p>\n<p><span 
 style="background-color: #ffffff\;">The Versal ACAP is a new platform offe
 ring from Xilinx that exploits leading edge 7nm semiconductor process tech
 nology with semiconductor innovation to create a new category of adaptive 
 SoCs. This portfolio of devices can be used to create Domain Specific Arch
 itectures that are scalable and optimized to meet a wide range of applicat
 ion requirements from end points to vehicles to infrastructure. 5G archite
 ctures requiring compute intensive functionality\, such as massive MIMO an
 d beamforming\, are key target applications that are enabled by Versal and
  its&rsquo\; silicon innovations.<br />Tools are a critical component of e
 nabling the developer community to leverage the full potential of Versal p
 latforms. Vitis Unified Software Platform\, combined with Vivado Design Su
 ite\, offers a comprehensive development environment and programming model
  that enables all developers\, including hardware and software engineers\,
  and data scientists to access the full potential of Versal ACAP. With Vit
 is\, developers can meet the growing challenges and unique requirements of
  their applications\, while continuing to work at an application level and
  develop in familiar programming languages &amp\; frameworks.<br />In this
  session\, equal time will be spent reviewing the benefits and features of
  both Versal devices and the Vitis tool flow with an emphasis on 5G applic
 ations.</span></p>
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