BEGIN:VCALENDAR
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PRODID:IEEE vTools.Events//EN
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DTSTART:20210314T030000
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DTSTAMP:20210224T214410Z
UID:DCD1FF2B-9D7F-4873-B278-838C25E8CCE1
DTSTART;TZID=Canada/Eastern:20210211T145000
DTEND;TZID=Canada/Eastern:20210211T155000
DESCRIPTION:The chiplet interface allows multiple silicon dies of various t
 echnologies and complexities to communicate efficiently using larger paral
 lel interconnects in a single package. The second layer of interconnect on
  the package (silicon or organic interposer) provides dense channels as we
 ll as low impedance power delivery paths between multiple independent powe
 r domains. Although the channels are very short and the I/O power can be r
 educed by an order of magnitude\, the huge increase in the transient curre
 nt in multiple dies and the unique clocking architecture makes the supply 
 noise and timing jitter the limiting factors in designing high-performance
  multi-die systems. This talk discusses the unique signal and power integr
 ity challenges of chiplet interfaces.\n\nSpeaker(s): Wendem Tsegaye Beyene
 \, \n\nVirtual: https://events.vtools.ieee.org/m/260643
LOCATION:Virtual: https://events.vtools.ieee.org/m/260643
ORGANIZER:durand.jarrettamor@ieee.org
SEQUENCE:5
SUMMARY:Design And Analysis Of Chiplet Interfaces For Heterogeneous Systems
URL;VALUE=URI:https://events.vtools.ieee.org/m/260643
X-ALT-DESC:Description: <br /><p><span style="font-size: 12pt\;">The chiple
 t interface allows multiple silicon dies of various technologies and compl
 exities to communicate efficiently using larger parallel interconnects in 
 a single package. The second layer of interconnect on the package (silicon
  or organic interposer) provides dense channels as well as low impedance p
 ower delivery paths between multiple independent power domains. Although t
 he channels are very short and the I/O power can be reduced by an order of
  magnitude\, the huge increase in the transient current in multiple dies a
 nd the unique clocking architecture makes the supply noise and timing jitt
 er the limiting factors in designing high-performance multi-die systems. T
 his talk discusses the unique signal and power integrity challenges of chi
 plet interfaces.</span></p>
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