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PRODID:IEEE vTools.Events//EN
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DTSTART:20210314T030000
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DTSTART:20211107T010000
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BEGIN:VEVENT
DTSTAMP:20210318T215036Z
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DTSTART;TZID=America/Los_Angeles:20210318T090000
DTEND;TZID=America/Los_Angeles:20210318T101500
DESCRIPTION:Many applications such as Digitally Modulated Radar (DMR)\, aut
 omotive ethernet\, 5G\, etc. require analog-to-digital converters (ADCs) w
 ith high-dynamic range as well as multi-GHz sample rates\, and at the same
  time\, the associated post-ADC signal processing requirements are driving
  the ADC implementations to sub-16nm process technologies. The challenges 
 associated with implementing Gs/s ADCs in sub-16nm process technologies ar
 e significant and include: precise clocking\, high-dynamic range with low 
 supply voltages\, Layout Dependent Effects (LDE)\, etc. Using Digitally Mo
 dulated Radar as the driving application\, example ADC architectures that 
 attempt to address these issues while taking best advantage of the sub-16n
 m process technologies will be presented. However\, extensive research is 
 still be needed to develop ADCs with the required performance at a reasona
 ble cost and that also yield well\, and industry and academia must coopera
 te and collaborate much more effectively in order to address this critical
  need.\n\nSpeaker(s): Dr. Doug Garrity\, \n\nSan Diego\, California\, Unit
 ed States\, Virtual: https://events.vtools.ieee.org/m/264718
LOCATION:San Diego\, California\, United States\, Virtual: https://events.v
 tools.ieee.org/m/264718
ORGANIZER:jshi@ieee.org
SEQUENCE:2
SUMMARY:Gs/s Analog-to-Digital Converters in sub-16nm Process Technologies 
URL;VALUE=URI:https://events.vtools.ieee.org/m/264718
X-ALT-DESC:Description: <br /><p>Many applications such as Digitally Modula
 ted Radar (DMR)\, automotive ethernet\, 5G\, etc. require analog-to-digita
 l converters (ADCs) with high-dynamic range as well as multi-GHz sample ra
 tes\, and at the same time\, the associated post-ADC signal processing req
 uirements are driving the ADC implementations to sub-16nm process technolo
 gies. The challenges associated with implementing Gs/s ADCs in sub-16nm pr
 ocess technologies are significant and include: precise clocking\, high-dy
 namic range with low supply voltages\, Layout Dependent Effects (LDE)\, et
 c. Using Digitally Modulated Radar as the driving application\, example AD
 C architectures that attempt to address these issues while taking best adv
 antage of the sub-16nm process technologies will be presented. However\, e
 xtensive research is still be needed to develop ADCs with the required per
 formance at a reasonable cost and that also yield well\, and industry and 
 academia must cooperate and collaborate much more effectively in order to 
 address this critical need.</p>
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